Design of a Low-power Computational Unit using a Pipelined Vedic Multiplier

The quest to minimize power consumption in portable battery-operated devices has led to the pursuit of innovative techniques for power reduction in digital circuits. Modern Central Processing Units (CPU) and graphics processing units incorporate powerful and complex computational units within their processors. The performance of the computational unit is a direct indication of the performance of the CPU. There has been considerable research in developing computational units to accomplish fast and power-efficient performance. One of the significant challenges in ASIC design is power dissipation. Low power design strategies that provide substantial power savings with reduced overhead in terms of delay are desirable. This research concentrates on the design of a computational unit with a pipelined Vedic multiplier, an adder/subtractor, and a logic module with operand isolation optimized for low power. The synthesis of the proposed computational unit was performed using 45 and 90 nm technology libraries in an Electronic Design Automation (EDA) Tool. The findings indicate that the proposed architecture exhibited reduced power and delay compared to existing designs.