TY - JOUR
T1 - Design of high speed 32-bit floating point multiplier using Urdhva Triyagbhyam sutra of vedic mathematics
AU - Sai Venkatramana Prasada, G. S.
AU - Seshikala, G.
AU - Niranjana, S.
PY - 2019/7/1
Y1 - 2019/7/1
N2 - Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.
AB - Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.
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U2 - 10.35940/ijrte.B1199.0782S319
DO - 10.35940/ijrte.B1199.0782S319
M3 - Article
AN - SCOPUS:85071250741
SN - 2277-3878
VL - 8
SP - 1064
EP - 1067
JO - International Journal of Recent Technology and Engineering
JF - International Journal of Recent Technology and Engineering
IS - 2 Special issue 3
ER -