Design of Low Power and High Speed 1-bit Full Adder for DSP Applications

Shaik Mohisena Tabassum; M. Venkata Kavya Sri; D. Bhanu Navya Sri; Shaik Muskaan; Satyajeet Sahoo; Aswini K. Samataray

doi:10.1109/APCI61480.2024.10616610

Design of Low Power and High Speed 1-bit Full Adder for DSP Applications

Shaik Mohisena Tabassum^*
, M. Venkata Kavya Sri
, D. Bhanu Navya Sri
, Shaik Muskaan
, Satyajeet Sahoo
, Aswini K. Samataray

^*Corresponding author for this work

Department of Electronics and Communication Engineering, Manipal Institute of Technology, Bengaluru

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This paper deals with the design of the full adder circuit using the Cadence virtuoso 180nm technology. The entire circuit of the full adder consists of generation of XOR- XNOR, sum and carry. The adder is implemented in such a way that it meets the specifications of full voltage output swing and less delay. The performance of the full adder is observed using the cadence tool. The circuit contains the characteristics of the novel circuit which is really essential in order to gain the utilization of it in real life applications.

Original language	English
Title of host publication	International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350363289
DOIs	https://doi.org/10.1109/APCI61480.2024.10616610
Publication status	Published - 2024
Event	2024 International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024 - Kannur, India Duration: 21-06-2024 → 22-06-2024

Publication series

Name	International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024

Conference

Conference	2024 International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024
Country/Territory	India
City	Kannur
Period	21-06-24 → 22-06-24

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Artificial Intelligence
Computer Networks and Communications
Energy Engineering and Power Technology
Renewable Energy, Sustainability and the Environment
Electrical and Electronic Engineering
Control and Optimization
Modelling and Simulation

Access to Document

10.1109/APCI61480.2024.10616610

Cite this

Tabassum, S. M., Sri, M. V. K., Sri, D. B. N., Muskaan, S., Sahoo, S., & Samataray, A. K. (2024). Design of Low Power and High Speed 1-bit Full Adder for DSP Applications. In International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024 (International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCI61480.2024.10616610

Tabassum, Shaik Mohisena ; Sri, M. Venkata Kavya ; Sri, D. Bhanu Navya et al. / Design of Low Power and High Speed 1-bit Full Adder for DSP Applications. International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024. Institute of Electrical and Electronics Engineers Inc., 2024. (International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024).

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title = "Design of Low Power and High Speed 1-bit Full Adder for DSP Applications",

abstract = "This paper deals with the design of the full adder circuit using the Cadence virtuoso 180nm technology. The entire circuit of the full adder consists of generation of XOR- XNOR, sum and carry. The adder is implemented in such a way that it meets the specifications of full voltage output swing and less delay. The performance of the full adder is observed using the cadence tool. The circuit contains the characteristics of the novel circuit which is really essential in order to gain the utilization of it in real life applications.",

author = "Tabassum, \{Shaik Mohisena\} and Sri, \{M. Venkata Kavya\} and Sri, \{D. Bhanu Navya\} and Shaik Muskaan and Satyajeet Sahoo and Samataray, \{Aswini K.\}",

note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024 ; Conference date: 21-06-2024 Through 22-06-2024",

year = "2024",

doi = "10.1109/APCI61480.2024.10616610",

language = "English",

series = "International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024",

address = "United States",

}

Tabassum, SM, Sri, MVK, Sri, DBN, Muskaan, S, Sahoo, S & Samataray, AK 2024, Design of Low Power and High Speed 1-bit Full Adder for DSP Applications. in International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024. International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024, Institute of Electrical and Electronics Engineers Inc., 2024 International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024, Kannur, India, 21-06-24. https://doi.org/10.1109/APCI61480.2024.10616610

Design of Low Power and High Speed 1-bit Full Adder for DSP Applications. / Tabassum, Shaik Mohisena; Sri, M. Venkata Kavya; Sri, D. Bhanu Navya et al.
International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024. Institute of Electrical and Electronics Engineers Inc., 2024. (International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Design of Low Power and High Speed 1-bit Full Adder for DSP Applications

AU - Tabassum, Shaik Mohisena

AU - Sri, M. Venkata Kavya

AU - Sri, D. Bhanu Navya

AU - Muskaan, Shaik

AU - Sahoo, Satyajeet

AU - Samataray, Aswini K.

PY - 2024

Y1 - 2024

N2 - This paper deals with the design of the full adder circuit using the Cadence virtuoso 180nm technology. The entire circuit of the full adder consists of generation of XOR- XNOR, sum and carry. The adder is implemented in such a way that it meets the specifications of full voltage output swing and less delay. The performance of the full adder is observed using the cadence tool. The circuit contains the characteristics of the novel circuit which is really essential in order to gain the utilization of it in real life applications.

AB - This paper deals with the design of the full adder circuit using the Cadence virtuoso 180nm technology. The entire circuit of the full adder consists of generation of XOR- XNOR, sum and carry. The adder is implemented in such a way that it meets the specifications of full voltage output swing and less delay. The performance of the full adder is observed using the cadence tool. The circuit contains the characteristics of the novel circuit which is really essential in order to gain the utilization of it in real life applications.

UR - https://www.scopus.com/pages/publications/85201418978

UR - https://www.scopus.com/pages/publications/85201418978#tab=citedBy

U2 - 10.1109/APCI61480.2024.10616610

DO - 10.1109/APCI61480.2024.10616610

M3 - Conference contribution

AN - SCOPUS:85201418978

T3 - International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024

BT - International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2024 International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024

Y2 - 21 June 2024 through 22 June 2024

ER -

Tabassum SM, Sri MVK, Sri DBN, Muskaan S, Sahoo S, Samataray AK. Design of Low Power and High Speed 1-bit Full Adder for DSP Applications. In International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024. Institute of Electrical and Electronics Engineers Inc. 2024. (International Conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024). doi: 10.1109/APCI61480.2024.10616610

Design of Low Power and High Speed 1-bit Full Adder for DSP Applications

Abstract

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UN SDGs

All Science Journal Classification (ASJC) codes

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