Design of Skewed CMOS Ring Oscillators with Controlled Frequency for On-Chip Clock Generation

This work aims to study the effect of variation in aspect ratio (Wp Wn) on the frequency of ring oscillator waveforms with constant gate size. Ring oscillator is designed using 11 identical NOT gates with different skews (downskewed, balanced, upskewed) cascaded in series with a feedback loop. The simulations are conducted in Cadence Virtuoso EDA tool using gpdk90 technology. Five ring oscillator circuits are designed each using 11 identical NOT gates with aspect ratios 1: 3,1: 2,1: 1,2: 1, and 3: 1 corresponding to Wp/ Wn of 0.33,0.5,1, 2, and 3, respectively, cascaded in series with a feedback loop. The five ring oscillator circuits are named R O1: 3, R O1: 2, R O1: 1, R O2: 1, and R O3: 1, with sub-script representing the aspect ratio (Wp/Wn) of the NOT gates used. Ring oscillators RO1: 3, RO1: 2, and RO1: 1 are downskewed, RO2: 1 is balanced skewed, and RO3: 1 is upskewed. Our results show that R O1: 3, R O1: 2, R O1: 1, R O2: 1, and RO3: 1 produced a square waveform with frequencies 43.73 MHz, 58.51 MHz, 68.15 MHz, 76.87 MHz, and 63.68 MHz, respectively. This shows that the aspect ratio has significant effect on the frequency of ring oscillator, and the idea of the aspect ratio can be used to design clock generator or Schmitt trigger circuits to produce square waves with desirable frequencies.