Design, Verification and Hardware Implementation of 4kB Synchronous FIFO for Automatic Vehicle Communication Applications

Sustainability in in-vehicle communication comprises the integration of wireless technology for faster and more reliable connectivity. Driverless vehicles need to schedule various tasks on a priority basis. The first-in-first-out (FIFO) data structure is critical for handling sensor data and communication information, and a memory queue is important for controlling data flow through organized read and write processes. This study focuses on the design, verification and synthesis of a FIFO with a size of 4k bytes. By operating on a single clock signal, synchronous FIFO enables smooth data transmission between a source and destination within the same clock domain. The designed FIFO resulted in an area of 41.401 mm ², a power dissipation of 0.506 mW and a critical path delay of 0.03 ps when a 15 nm open-cell library from Nangate was used. The design is also implemented using an Arria II field programmable gate array (FPGA), which results in a maximum clock frequency of 33.33 GHz.