TY - GEN
T1 - Device Analysis of Vertically Stacked GAA Nanosheet FET at Advanced Technology Node
AU - Kumar, Aruru Sai
AU - Deekshana, M.
AU - Sreenivasulu, V. Bharath
AU - Kumari, N. Aruna
AU - Shanthi, G.
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Moore's law indicates that several technological developments are currently being digested. Since switching from a simple MOSFET built with a single control gate to one with numerous control gates, the device's controllability has significantly enhanced. In this paper, the device-level simulation of vertically stacked GAA nanosheet FET is performed for which the various geometrical variations are calibrated. This research Paper examines the impact of these geometrical variations on the performance of the device. The most prominent parameters like ION, IOFF, SS, DIBL, switching ratio, and Threshold voltage values are analyzed. For the device to be considered to have better performance ION should be maximum, IOFF should be minimum. Hence to obtain this the thickness of the nanosheet is varied on the scale of 5nm to 9nm and the width is varied from 10nm to 50nm. The device simulation and analysis are performed using the Visual TCAD - 3D Cogenda tool.
AB - Moore's law indicates that several technological developments are currently being digested. Since switching from a simple MOSFET built with a single control gate to one with numerous control gates, the device's controllability has significantly enhanced. In this paper, the device-level simulation of vertically stacked GAA nanosheet FET is performed for which the various geometrical variations are calibrated. This research Paper examines the impact of these geometrical variations on the performance of the device. The most prominent parameters like ION, IOFF, SS, DIBL, switching ratio, and Threshold voltage values are analyzed. For the device to be considered to have better performance ION should be maximum, IOFF should be minimum. Hence to obtain this the thickness of the nanosheet is varied on the scale of 5nm to 9nm and the width is varied from 10nm to 50nm. The device simulation and analysis are performed using the Visual TCAD - 3D Cogenda tool.
UR - https://www.scopus.com/pages/publications/85168690597
UR - https://www.scopus.com/pages/publications/85168690597#tab=citedBy
U2 - 10.1109/ACCESS57397.2023.10199820
DO - 10.1109/ACCESS57397.2023.10199820
M3 - Conference contribution
AN - SCOPUS:85168690597
T3 - ACCESS 2023 - 2023 3rd International Conference on Advances in Computing, Communication, Embedded and Secure Systems
SP - 274
EP - 279
BT - ACCESS 2023 - 2023 3rd International Conference on Advances in Computing, Communication, Embedded and Secure Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 3rd International Conference on Advances in Computing, Communication, Embedded and Secure Systems, ACCESS 2023
Y2 - 18 May 2023 through 20 May 2023
ER -