TY - GEN
T1 - Device Design Aware and Interface Thermal Resistance Assisted Self-Heating Analysis in Nanosheet FET
AU - Rathore, Sunil
AU - Banchhor, Shashank Kumar
AU - Jaisawal, Rajeewa Kumar
AU - Dixit, Ankit
AU - Kondekar, Pravin
AU - Bagga, Navjeet
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - The nanoscaled geometrical confinement of the Nanosheet FET (NSHFET) has severely aggravated the self-heating effect, affecting the device's characteristics, such as lattice temperature, thermal contact resistance, and drive current. In this paper, we investigated the self-heating effect (SHE) in the NSHFET using well-calibrated TCAD models. We analyzed (i) the behavior of spatial device lattice temperature (TD) gradient in a gate-all-around (GAA) NSHFET; (ii) the impact of varying the drain, source, and gate electrode thermal contact resistances $(\mathrm{R}_{\text{th DSG}})$. (iii) a fair comparison of electrical and thermal characteristics of SOI FinFET, bulk FinFET, and NSHFET based on the percentage change in subthreshold slope (SS), drain-induced barrier lowering (DIBL), drain current, etc. Further, we proposed the design guideline to mitigate SHE-induced thermal degradation in Nanosheet FET.
AB - The nanoscaled geometrical confinement of the Nanosheet FET (NSHFET) has severely aggravated the self-heating effect, affecting the device's characteristics, such as lattice temperature, thermal contact resistance, and drive current. In this paper, we investigated the self-heating effect (SHE) in the NSHFET using well-calibrated TCAD models. We analyzed (i) the behavior of spatial device lattice temperature (TD) gradient in a gate-all-around (GAA) NSHFET; (ii) the impact of varying the drain, source, and gate electrode thermal contact resistances $(\mathrm{R}_{\text{th DSG}})$. (iii) a fair comparison of electrical and thermal characteristics of SOI FinFET, bulk FinFET, and NSHFET based on the percentage change in subthreshold slope (SS), drain-induced barrier lowering (DIBL), drain current, etc. Further, we proposed the design guideline to mitigate SHE-induced thermal degradation in Nanosheet FET.
UR - https://www.scopus.com/pages/publications/85160568014
UR - https://www.scopus.com/pages/publications/85160568014#tab=citedBy
U2 - 10.1109/ICEE56203.2022.10117683
DO - 10.1109/ICEE56203.2022.10117683
M3 - Conference contribution
AN - SCOPUS:85160568014
T3 - 2022 IEEE International Conference on Emerging Electronics, ICEE 2022
BT - 2022 IEEE International Conference on Emerging Electronics, ICEE 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE International Conference on Emerging Electronics, ICEE 2022
Y2 - 11 December 2022 through 14 December 2022
ER -