Digital-logic assessment of junctionless twin gate trench channel (JL-TGTC) MOSFET for memory circuit applications

Ajay Kumar; Neha Gupta; Aditya Jain; Rajeev Gupta; Bharat Choudhary; Kaushal Kumar; Amit Kumar Goyal; Yehia Massoud

doi:10.1016/j.memori.2023.100087

Digital-logic assessment of junctionless twin gate trench channel (JL-TGTC) MOSFET for memory circuit applications

Ajay Kumar^*
, Neha Gupta
, Aditya Jain
, Rajeev Gupta
, Bharat Choudhary
, Kaushal Kumar
, Amit Kumar Goyal
, Yehia Massoud

^*Corresponding author for this work

Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal

Research output: Contribution to journal › Article › peer-review

8 Citations (Scopus)

Abstract

In this paper, Junctionless Twin Gate Trench Channel (JL-TGTC) MOSFET with individual gate control is realized. The device gives full functionality of 2-input digital ‘AND’ and ‘NAND’ logics. The simulation depicts the results in the form of various parameters such as cutoff current, transfer characteristics, and potential profiles. All the simulations regarding device structure and functionality are done on TCAD. This new type of MOS device has improved applicability in low-voltage digital electronics such as sequential circuits etc.

Original language	English
Article number	100087
Journal	Memories - Materials, Devices, Circuits and Systems
Volume	6
DOIs	https://doi.org/10.1016/j.memori.2023.100087
Publication status	Published - 12-2023

All Science Journal Classification (ASJC) codes

Engineering (miscellaneous)
Computational Mechanics
General Materials Science
Electrical and Electronic Engineering
Computer Science (miscellaneous)

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10.1016/j.memori.2023.100087

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title = "Digital-logic assessment of junctionless twin gate trench channel (JL-TGTC) MOSFET for memory circuit applications",

abstract = "In this paper, Junctionless Twin Gate Trench Channel (JL-TGTC) MOSFET with individual gate control is realized. The device gives full functionality of 2-input digital {\textquoteleft}AND{\textquoteright} and {\textquoteleft}NAND{\textquoteright} logics. The simulation depicts the results in the form of various parameters such as cutoff current, transfer characteristics, and potential profiles. All the simulations regarding device structure and functionality are done on TCAD. This new type of MOS device has improved applicability in low-voltage digital electronics such as sequential circuits etc.",

author = "Ajay Kumar and Neha Gupta and Aditya Jain and Rajeev Gupta and Bharat Choudhary and Kaushal Kumar and Goyal, \{Amit Kumar\} and Yehia Massoud",

note = "Publisher Copyright: {\textcopyright} 2023 The Authors",

year = "2023",

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doi = "10.1016/j.memori.2023.100087",

language = "English",

volume = "6",

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T1 - Digital-logic assessment of junctionless twin gate trench channel (JL-TGTC) MOSFET for memory circuit applications

AU - Kumar, Ajay

AU - Gupta, Neha

AU - Jain, Aditya

AU - Gupta, Rajeev

AU - Choudhary, Bharat

AU - Kumar, Kaushal

AU - Goyal, Amit Kumar

AU - Massoud, Yehia

PY - 2023/12

Y1 - 2023/12

N2 - In this paper, Junctionless Twin Gate Trench Channel (JL-TGTC) MOSFET with individual gate control is realized. The device gives full functionality of 2-input digital ‘AND’ and ‘NAND’ logics. The simulation depicts the results in the form of various parameters such as cutoff current, transfer characteristics, and potential profiles. All the simulations regarding device structure and functionality are done on TCAD. This new type of MOS device has improved applicability in low-voltage digital electronics such as sequential circuits etc.

AB - In this paper, Junctionless Twin Gate Trench Channel (JL-TGTC) MOSFET with individual gate control is realized. The device gives full functionality of 2-input digital ‘AND’ and ‘NAND’ logics. The simulation depicts the results in the form of various parameters such as cutoff current, transfer characteristics, and potential profiles. All the simulations regarding device structure and functionality are done on TCAD. This new type of MOS device has improved applicability in low-voltage digital electronics such as sequential circuits etc.

UR - https://www.scopus.com/pages/publications/85195177073

UR - https://www.scopus.com/pages/publications/85195177073#tab=citedBy

U2 - 10.1016/j.memori.2023.100087

DO - 10.1016/j.memori.2023.100087

M3 - Article

AN - SCOPUS:85195177073

SN - 2773-0646

VL - 6

JO - Memories - Materials, Devices, Circuits and Systems

JF - Memories - Materials, Devices, Circuits and Systems

M1 - 100087

ER -

Digital-logic assessment of junctionless twin gate trench channel (JL-TGTC) MOSFET for memory circuit applications

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