Dynamic Branch Prediction for Embedded System Applications

As Branch prediction is a performance improving technique adopted in modern processor architectures. Conventional prediction techniques have advantages such as power efficiency and speedy lookup, but with high miss-prediction rate. Neural network based and two level predictions are complex but offer improved accuracy. But disadvantage of these methods are higher power consumption, exponential increase in the complexity and time of execution ranging from 3 - 5 cycles. Optimized branch prediction should have least miss rate, lower power consumption and fewer complexes. It should use minimum resources also. In this paper the algorithm has been implemented for branch prediction which is particularly useful for superscalar or pipelined processors. With current branch prediction algorithms, the success rate of 99% can be achieved but not more than this as some times the prediction fails and whole pipe has to be flushed again. The method that has been currently implemented with increase in the hardware will always predict the branch correctly. The algorithm is very efficient in reducing time and power consumption while implementing code for processor architecture applications used in embedded systems.