Effective Design of a High-Speed, Low-Power Hybrid Adder for Computing Systems Using XOR-XNOR Cells

While designing any VLSI circuit, the main parameters to be considered are speed and power consumption. Because of the rapid advancement of technology, power consumption has emerged as a significant concern while building circuits. In designing a circuit with less power consumption, maintaining great performance at fast speed is the most demanding aspect. Generally, many techniques exist for reduction of power consumption. Different design layers, such as the circuit level and the algorithmic level, can be used to accomplish this goal. This chapter represents a circuit design at circuit level with power optimization. In this, design of a hybrid full adder using different logic styles is suggested. The logic styles used to design a hybrid adder in this chapter are pass transistor logic (PTL), transmission gate logic (TGL), and CMOS logic. The main aim of this work is to design a low power, high speed XOR-XNOR cell-based hybrid adder for different computation systems. The XOR-XNOR cell is used to determine the efficiency of the full adder work in terms of different parameters like power consumption, speed, performance, etc. The Cadence Virtuoso tool is utilized to assess the circuit performance in 90 nm CMOS technology. The effectiveness of the current design is compared with the recent existing methods. It is found from the performance comparison that the proposed design has a reduction of delay by more than 50% than the existing full adders and the power delay product (PDP) is also reduced to 42.36%. Hence, the proposed full adder can be used for low power applications and computations.