Abstract
This paper comprises the design of the approximate multiplier using the Xilinx Vivado software. The whole design consists of a decoder-logic where the output is obtained as partial products and these are given to the ripple carry adder to get the final product. The hardware verification of the design is done using FPGA board - ARTY A7. The design is written in Verilog using the gate level modelling. This can be used for the various image processing applications.
| Original language | English |
|---|---|
| Title of host publication | 2025 2nd International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2025 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9798331537791 |
| DOIs | |
| Publication status | Published - 2025 |
| Event | 2nd International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2025 - Bhubaneswar, India Duration: 05-09-2025 → 07-09-2025 |
Publication series
| Name | 2025 2nd International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2025 |
|---|
Conference
| Conference | 2nd International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2025 |
|---|---|
| Country/Territory | India |
| City | Bhubaneswar |
| Period | 05-09-25 → 07-09-25 |
UN SDGs
This output contributes to the following UN Sustainable Development Goals (SDGs)
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SDG 7 Affordable and Clean Energy
All Science Journal Classification (ASJC) codes
- Artificial Intelligence
- Computer Vision and Pattern Recognition
- Information Systems and Management
- Energy Engineering and Power Technology
- Renewable Energy, Sustainability and the Environment
- Electrical and Electronic Engineering
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