Gate Stack Analysis of Junctionless Multi-Bridge-Channel FETs for Sub-3nm Chips

In the proposed work, we have investigated the potential of the nanosheet FET design and temperature analysis at advanced nodes. Our investigation shows that the variation of gate length (L_G) from 30nm down to 3nm, accompanied by using different gate dielectric materials, like silicon dioxide (only SiO₂(3nm)) and hafnium dioxide (HfO₂) i.e., (SiO₂ (2nm) + HfO₂ (1nm)). The analysis is done at Linear (Ohmic) region to observe variable resistor for amplifiers or analog applications and saturation region to analyze the voltage controlled current sources (VCCS) applications. To comprehensively evaluate the electrical performance of the devices at the nano regime, quantum models are invoked to get accurate metrics like sub-threshold swing (SS), drain induced barrier lowering (DIBL), ON current (I_ON), OFF current (I_OFF), and I_ON/I_OFF ratio. Interestingly, even at the ultra-scaled dimensions of 5nm and 3nm, our devices exhibited remarkable electrical properties, with I_OFF reaching 10¹³ at 5nm and 10¹¹ at 3nm, while I_ON maintained a level of ∼10⁶ at both dimensions when HfO₂ gate stack is employed as the gate dielectric material. Our findings indicate that the integration of high-k materials becomes imperative for achieving superior device performance, particularly at reduced L_G values. Moreover, we explored the scaling flexibility of the transistors by investigating additional parameters such as transconductance (g_m) and transconductance generation factor (TGF). The impact of scaling of nanosheet FET towards temperature is also analyzed.