TY - JOUR
T1 - Generalized switched-capacitor multilevel inverter topology with self-balancing capacitors
AU - Jena, Kasinath
AU - Panigrahi, Chinmoy Kumar
AU - Gupta, Krishna Kumar
AU - Kumar, Dhananjay
AU - Dewangan, Niraj Kumar
N1 - Publisher Copyright:
© 2022, The Author(s) under exclusive licence to The Korean Institute of Power Electronics.
PY - 2022/9
Y1 - 2022/9
N2 - This paper presents a switched-capacitor topology with fewer switching components and reduced voltage stresses. The circuit contains eight switches and two capacitors to generate a five-level voltage waveform. This paper provides in-depth descriptions of the structural design, operation, and loss analysis. Inherently self-balanced capacitors are utilized in the proposed topology, which eliminates the need for additional charge balancing circuits and sensors. The control action was implemented using a simple logic-based multicarrier pulse width modulation (PWM) strategy. A brief comparative analysis with state-of-the-art topologies has been presented to demonstrate the merits of the developed topology. Finally, the feasibility and efficacy of the suggested topology have been evaluated using simulation and experimental testing to ensure that it is both feasible and effective.
AB - This paper presents a switched-capacitor topology with fewer switching components and reduced voltage stresses. The circuit contains eight switches and two capacitors to generate a five-level voltage waveform. This paper provides in-depth descriptions of the structural design, operation, and loss analysis. Inherently self-balanced capacitors are utilized in the proposed topology, which eliminates the need for additional charge balancing circuits and sensors. The control action was implemented using a simple logic-based multicarrier pulse width modulation (PWM) strategy. A brief comparative analysis with state-of-the-art topologies has been presented to demonstrate the merits of the developed topology. Finally, the feasibility and efficacy of the suggested topology have been evaluated using simulation and experimental testing to ensure that it is both feasible and effective.
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U2 - 10.1007/s43236-022-00456-4
DO - 10.1007/s43236-022-00456-4
M3 - Article
AN - SCOPUS:85130450595
SN - 1598-2092
VL - 22
SP - 1617
EP - 1626
JO - Journal of Power Electronics
JF - Journal of Power Electronics
IS - 9
ER -