High level modeling of physical layer noise parameters using SystemC

Prem Kumar Lohani; K. Ranjani; R. Ravi Shankar; C. Sundaresan; C. V.S. Chaitanya

doi:10.1109/ICE2T.2014.7006275

High level modeling of physical layer noise parameters using SystemC

Prem Kumar Lohani, K. Ranjani, R. Ravi Shankar, C. Sundaresan, C. V.S. Chaitanya

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Systemverilog and SystemC are extensively used for design and Verification in VLSI industry. This paper propose a method to combine SystemVerilog and SystemC code in a single hardware/software simulation which allows design teams to leverage abstract representations of system function as it increases system simulations speed. Both languages interoperate through an intermediate layer of abstraction known as Transaction Level Models (TLMs). This paper develops Universal Verification Methodology (UVM) TLM environment for SV and SC communication in the system modeling.

Original language	English
Title of host publication	2014 4th International Conference on Engineering Technology and Technopreneuship, ICE2T 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	344-347
Number of pages	4
Volume	2014-August
ISBN (Electronic)	9781479946211
DOIs	https://doi.org/10.1109/ICE2T.2014.7006275
Publication status	Published - 09-01-2015
Event	2014 4th International Conference on Engineering Technology and Technopreneuship, ICE2T 2014 - Kuala Lumpur, Malaysia Duration: 27-08-2014 → 29-08-2014

Conference

Conference	2014 4th International Conference on Engineering Technology and Technopreneuship, ICE2T 2014
Country/Territory	Malaysia
City	Kuala Lumpur
Period	27-08-14 → 29-08-14

All Science Journal Classification (ASJC) codes

Engineering(all)
Management of Technology and Innovation
Computer Science Applications

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10.1109/ICE2T.2014.7006275

Cite this

Lohani, P. K., Ranjani, K., Shankar, R. R., Sundaresan, C., & Chaitanya, C. V. S. (2015). High level modeling of physical layer noise parameters using SystemC. In 2014 4th International Conference on Engineering Technology and Technopreneuship, ICE2T 2014 (Vol. 2014-August, pp. 344-347). [7006275] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICE2T.2014.7006275

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title = "High level modeling of physical layer noise parameters using SystemC",

abstract = "Systemverilog and SystemC are extensively used for design and Verification in VLSI industry. This paper propose a method to combine SystemVerilog and SystemC code in a single hardware/software simulation which allows design teams to leverage abstract representations of system function as it increases system simulations speed. Both languages interoperate through an intermediate layer of abstraction known as Transaction Level Models (TLMs). This paper develops Universal Verification Methodology (UVM) TLM environment for SV and SC communication in the system modeling.",

author = "Lohani, {Prem Kumar} and K. Ranjani and Shankar, {R. Ravi} and C. Sundaresan and Chaitanya, {C. V.S.}",

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doi = "10.1109/ICE2T.2014.7006275",

language = "English",

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booktitle = "2014 4th International Conference on Engineering Technology and Technopreneuship, ICE2T 2014",

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note = "2014 4th International Conference on Engineering Technology and Technopreneuship, ICE2T 2014 ; Conference date: 27-08-2014 Through 29-08-2014",

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Lohani, PK, Ranjani, K, Shankar, RR, Sundaresan, C & Chaitanya, CVS 2015, High level modeling of physical layer noise parameters using SystemC. in 2014 4th International Conference on Engineering Technology and Technopreneuship, ICE2T 2014. vol. 2014-August, 7006275, Institute of Electrical and Electronics Engineers Inc., pp. 344-347, 2014 4th International Conference on Engineering Technology and Technopreneuship, ICE2T 2014, Kuala Lumpur, Malaysia, 27-08-14. https://doi.org/10.1109/ICE2T.2014.7006275

High level modeling of physical layer noise parameters using SystemC. / Lohani, Prem Kumar; Ranjani, K.; Shankar, R. Ravi et al.

2014 4th International Conference on Engineering Technology and Technopreneuship, ICE2T 2014. Vol. 2014-August Institute of Electrical and Electronics Engineers Inc., 2015. p. 344-347 7006275.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - Systemverilog and SystemC are extensively used for design and Verification in VLSI industry. This paper propose a method to combine SystemVerilog and SystemC code in a single hardware/software simulation which allows design teams to leverage abstract representations of system function as it increases system simulations speed. Both languages interoperate through an intermediate layer of abstraction known as Transaction Level Models (TLMs). This paper develops Universal Verification Methodology (UVM) TLM environment for SV and SC communication in the system modeling.

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Y2 - 27 August 2014 through 29 August 2014

ER -

High level modeling of physical layer noise parameters using SystemC

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All Science Journal Classification (ASJC) codes

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