High Speed Signed 8-bit Multiplier using Booth Encoding and Dadda Tree Architecture

The architectural design of an 8-bit signed multiplier optimized for delay performance is implemented using Radix-4 Booth encoding and Dadda tree reduction techniques. The integration of Booth encoding reduces the number of partial products, while the Dadda reduction structure minimizes the number of logic levels during partial product accumulation, resulting in improved computation speed. The proposed multiplier is modeled using Verilog hardware description language and verified through simulation using Cadence NC-Sim. The ASIC synthesis is performed using Cadence Genus, and physical design is completed in Cadence Innovus targeting both 180 nm and 45 nm technology nodes. The complete RTL to GDSII flow is executed to evaluate the design in terms of delay, and power consumption. Comparative analysis with existing Booth and Baugh-Wooley multiplier architectures highlights a substantial improvement in delay with marginal trade-offs in power. At 180 nm, the proposed multiplier achieves up to 58.65% delay reduction compared to existing designs. At 45 nm, the improvement is even more significant, reaching 75.22%, demonstrating the architecture's effectiveness in timing-critical applications. The proposed multiplier demonstrates efficient performance for high-speed and low-latency applications. The design is well-suited for integration into DSP blocks, embedded processors, and AI hardware accelerators where fast arithmetic computation is essential. The proposed work addresses Sustainable Developmental Goals 4 and 9.