Impact of Aspect Ratio on Propagation Delay and Parasitics in CMOS Inverters: A Cadence Simulation Study

This research focuses on the study of effect of aspect ratio on the propagation delay and parasitic resistance and capacitance of CMOS inverter circuit. Cadence simulation tool with technology file gpdk90 is used for the simulation of this research. Initially, using Virtuoso tool the schematic of CMOS inverter is designed with different WL ratios 1: 2.45,1: 1, and 2.45:1 corresponding to aspect ratios 0.4081,1 and 2.45, respectively. It was found that the aspect ratio of 2.45 produced the lease propagation delay as compared to 1 and 0.4081 thereby, indicating that the aspect ratio of 2.45 performs much faster with minimal propagation delay. Furthermore, using Asura tool the layout of CMOS inverter with different aspect ratios are designed to determine the parasitic resistance and capacitance. These parasitics were determined at the input node and the output node for all three aspect ratios. It was found that the input parasitic resistance marginally changed. However, the output parasitic resistance was found to be 342.1 m Ω, 678.9 m Ω and 808.8 m Ω for aspect ratios 2.45,1 and 0.4081, respectively. In addition, the input parasitic capacitance was found to be 35.36 aF, 3.19 aF and 54.15 aF for aspect ratios 0.4081,1 and 2.45, respectively. Furthermore, the output parasitic capacitance was found to be 42.89 aF, 60.16 aF and 67.66 aF for aspect ratios 0.4081,1 and 2.45, respectively.