TY - GEN
T1 - Impact of Temperature on NDR Characteristics of a Negative Capacitance FinFET
T2 - 26th International Symposium on VLSI Design and Test, VDAT 2022
AU - Jaisawal, Rajeewa Kumar
AU - Rathore, Sunil
AU - Kondekar, P. N.
AU - Bagga, Navjeet
N1 - Publisher Copyright:
© 2022, The Author(s), under exclusive license to Springer Nature Switzerland AG.
PY - 2022
Y1 - 2022
N2 - Negative Differential Resistance (NDR) is an inherent property of Negative Capacitance (NC) based devices, i.e., a decrease in the drain current (ID) with increasing drain voltage (VDS). The analysis of NC-based devices in TCAD is strongly dependent on the reliable choice of the Landau parameters (α, β, γ, ρ, g). In this paper, using well-calibrated TCAD models, we investigated: (i) the influence of the temperature on the Landau parameters (primarily on α); (ii) the dependency of NDR on ‘α’ using a semi-empirical model; (iii) how does the change in temperature modulates the NDR region of the NC-FinFET; (iv) the electrical characteristics of NDR-free NC-FinFET. In the proposed study, we have taken the silicon (Si) doped HfO2 as a ferroelectric (FE) layer in the gate stack of the baseline FinFET to realize NC-FinFET. The impact of varying FE layer thickness and temperature on the NC regime is thoroughly investigated.
AB - Negative Differential Resistance (NDR) is an inherent property of Negative Capacitance (NC) based devices, i.e., a decrease in the drain current (ID) with increasing drain voltage (VDS). The analysis of NC-based devices in TCAD is strongly dependent on the reliable choice of the Landau parameters (α, β, γ, ρ, g). In this paper, using well-calibrated TCAD models, we investigated: (i) the influence of the temperature on the Landau parameters (primarily on α); (ii) the dependency of NDR on ‘α’ using a semi-empirical model; (iii) how does the change in temperature modulates the NDR region of the NC-FinFET; (iv) the electrical characteristics of NDR-free NC-FinFET. In the proposed study, we have taken the silicon (Si) doped HfO2 as a ferroelectric (FE) layer in the gate stack of the baseline FinFET to realize NC-FinFET. The impact of varying FE layer thickness and temperature on the NC regime is thoroughly investigated.
UR - https://www.scopus.com/pages/publications/85145007847
UR - https://www.scopus.com/pages/publications/85145007847#tab=citedBy
U2 - 10.1007/978-3-031-21514-8_9
DO - 10.1007/978-3-031-21514-8_9
M3 - Conference contribution
AN - SCOPUS:85145007847
SN - 9783031215131
T3 - Communications in Computer and Information Science
SP - 97
EP - 106
BT - VLSI Design and Test - 26th International Symposium, VDAT 2022, Revised Selected Papers
A2 - Shah, Ambika Prasad
A2 - Dasgupta, Sudeb
A2 - Darji, Anand
A2 - Tudu, Jaynarayan
PB - Springer Science and Business Media Deutschland GmbH
Y2 - 17 July 2022 through 19 July 2022
ER -