Implementation of interleaved dual boost converter utilizing FPGA for PWM

S. Suraj; Sarun Soman; J. J. Jijesh

doi:10.1109/RTEICT.2016.7807787

Implementation of interleaved dual boost converter utilizing FPGA for PWM

S. Suraj
, Sarun Soman
, J. J. Jijesh

Department of Electrical and Electronics Engineering, Manipal Institute of Technology, Manipal

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Citations (Scopus)

Abstract

Boost converter with high power has turned into the key part of the power framework that enables power to be completely used. The novel way to accomplish a decreased current ripple and voltage ripple for dc chopper is actualized. Typical boost converter is interleaved to stop high input current stress on the switches. Interleaved Dual Boost Converter has two boost converter worked in parallel and controlled utilizing interleaved strategy with same frequency and phase shift. This method permits assembling a high productive and compact converter. In this paper different parameters of the interleaved dual boost converter are contrasted with a conventional boost converter for an output of 70V, 2A. The outcomes demonstrate that this converter accomplishes a superior performance.

Original language	English
Title of host publication	2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	79-83
Number of pages	5
ISBN (Electronic)	9781509007745
DOIs	https://doi.org/10.1109/RTEICT.2016.7807787
Publication status	Published - 05-01-2017
Event	1st IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Bangalore, India Duration: 20-05-2016 → 21-05-2016

Publication series

Name	2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings

Conference

Conference	1st IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016
Country/Territory	India
City	Bangalore
Period	20-05-16 → 21-05-16

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Computer Science Applications
Information Systems
Electrical and Electronic Engineering

Access to Document

10.1109/RTEICT.2016.7807787

Cite this

Suraj, S., Soman, S., & Jijesh, J. J. (2017). Implementation of interleaved dual boost converter utilizing FPGA for PWM. In 2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings (pp. 79-83). Article 7807787 (2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RTEICT.2016.7807787

Suraj, S. ; Soman, Sarun ; Jijesh, J. J. / Implementation of interleaved dual boost converter utilizing FPGA for PWM. 2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 79-83 (2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings).

@inproceedings{015d414547de4bf096db289e62e4a4b4,

title = "Implementation of interleaved dual boost converter utilizing FPGA for PWM",

abstract = "Boost converter with high power has turned into the key part of the power framework that enables power to be completely used. The novel way to accomplish a decreased current ripple and voltage ripple for dc chopper is actualized. Typical boost converter is interleaved to stop high input current stress on the switches. Interleaved Dual Boost Converter has two boost converter worked in parallel and controlled utilizing interleaved strategy with same frequency and phase shift. This method permits assembling a high productive and compact converter. In this paper different parameters of the interleaved dual boost converter are contrasted with a conventional boost converter for an output of 70V, 2A. The outcomes demonstrate that this converter accomplishes a superior performance.",

author = "S. Suraj and Sarun Soman and Jijesh, \{J. J.\}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 1st IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 ; Conference date: 20-05-2016 Through 21-05-2016",

year = "2017",

month = jan,

day = "5",

doi = "10.1109/RTEICT.2016.7807787",

language = "English",

series = "2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "79--83",

booktitle = "2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings",

address = "United States",

}

Suraj, S, Soman, S & Jijesh, JJ 2017, Implementation of interleaved dual boost converter utilizing FPGA for PWM. in 2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings., 7807787, 2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 79-83, 1st IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016, Bangalore, India, 20-05-16. https://doi.org/10.1109/RTEICT.2016.7807787

Implementation of interleaved dual boost converter utilizing FPGA for PWM. / Suraj, S.; Soman, Sarun; Jijesh, J. J.
2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. p. 79-83 7807787 (2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Implementation of interleaved dual boost converter utilizing FPGA for PWM

AU - Suraj, S.

AU - Soman, Sarun

AU - Jijesh, J. J.

PY - 2017/1/5

Y1 - 2017/1/5

N2 - Boost converter with high power has turned into the key part of the power framework that enables power to be completely used. The novel way to accomplish a decreased current ripple and voltage ripple for dc chopper is actualized. Typical boost converter is interleaved to stop high input current stress on the switches. Interleaved Dual Boost Converter has two boost converter worked in parallel and controlled utilizing interleaved strategy with same frequency and phase shift. This method permits assembling a high productive and compact converter. In this paper different parameters of the interleaved dual boost converter are contrasted with a conventional boost converter for an output of 70V, 2A. The outcomes demonstrate that this converter accomplishes a superior performance.

AB - Boost converter with high power has turned into the key part of the power framework that enables power to be completely used. The novel way to accomplish a decreased current ripple and voltage ripple for dc chopper is actualized. Typical boost converter is interleaved to stop high input current stress on the switches. Interleaved Dual Boost Converter has two boost converter worked in parallel and controlled utilizing interleaved strategy with same frequency and phase shift. This method permits assembling a high productive and compact converter. In this paper different parameters of the interleaved dual boost converter are contrasted with a conventional boost converter for an output of 70V, 2A. The outcomes demonstrate that this converter accomplishes a superior performance.

UR - https://www.scopus.com/pages/publications/85014991542

UR - https://www.scopus.com/pages/publications/85014991542#tab=citedBy

U2 - 10.1109/RTEICT.2016.7807787

DO - 10.1109/RTEICT.2016.7807787

M3 - Conference contribution

AN - SCOPUS:85014991542

T3 - 2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings

SP - 79

EP - 83

BT - 2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1st IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016

Y2 - 20 May 2016 through 21 May 2016

ER -

Suraj S, Soman S, Jijesh JJ. Implementation of interleaved dual boost converter utilizing FPGA for PWM. In 2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. p. 79-83. 7807787. (2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings). doi: 10.1109/RTEICT.2016.7807787

Implementation of interleaved dual boost converter utilizing FPGA for PWM

Abstract

Publication series

Conference

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this