Investigation of geometrical impact on a P⁺ buried negative capacitance SOI FET

In this paper, we proposed a novel p⁺ buried negative capacitance (NC) silicon-on-insulator (SOI) FET and investigated the impact of various device parameter variations on device performances. The placement of the p⁺ buried layers below the source/drain (S/D) pads restricts the electron conduction in the OFF state, thereby reducing the OFF current (I_OFF) with the least effect on the ON-current (I_ON). The proposed device structure effectively reduces the gate capacitance, providing better DC and analog/RF characteristics. In our proposed study, we separately discussed the effect of NC and impact ionization by turning the models on and off during simulation. Further, we discussed the impact of geometrical parameters of the proposed device, such as channel lengths, channel thickness, extension lengths, etc. on the device's electrical characteristics.