Low-area low-power parallel prefix adder based on modified ling equations

For the design and implementation of general purpose processors, addition plays an important role. Speed of an adder is one of the key factor that influences the performance of the system. Parallel prefix adders are one of the best solution for this, they are also suitable for VLSI implementation. Here in this paper parallel prefix adders based on modified ling equation have been proposed for 8-bit, 16-bit and 32-bit. Logic gates can be reduced using the proposed method that leads to reduction of area and power. The proposed adder is implemented using 90 nm and 180nm CMOS technology and compared with, other adopted adders. Synthesis results reveal that the proposed adder can achieve minimum area saving of 10% and power saving of 6%.