Machine Learning-Based Power Analysis of RISC-V Processor

The reduced instruction set computer, instruction set architecture, is a growingly well-liked development environment for both hardware and software. In this study, we investigate the power consumption of this processor for various operations performed using a standard synthesis process and the random forest (RF) method, a machine learning algorithm. It helps in estimating the power budget of integrated circuits at the initial stages of the design development and aims at energy efficiency designs for sustainable portable devices. A SystemVerilog description of the architecture is written and used to obtain the circuit using Genus. The leakage power, internal power, and switching power for various input vectors are analyzed, and the power report is generated. The average Pearson coefficient of 0.18 suggests that usage of the RF method with supervised learning was found to produce power estimation equivalent to that of the conventional method.