Abstract
This paper describes the memory architecture to improve the data transfer and storage in a small satellite. The main objective during the design stage of the architecture is to find a good balance between power consumption, cost, reliability and data processing capability. These variables directly impact each other, and it is important to achieve a suitable balance. For this, a low power flash memory is selected in conjunction with a faster static random access memory to improve the performance of the on-board computer on the satellite. In-built buffers of flash are suitably used to improve system performance. An extensive study of timing requirements to store data in memory is done. A comparison of performance at different voltage levels above the required minimum is done to get a balance between the required speed of programming the memory and power consumption. A highly modular and optimized algorithm is proposed for data transfer and storage which can be easily incorporated into a real time operating system. A method to further save the power is proposed by switching the flash memory to the power saving mode when its usage is not required.
Original language | English |
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Title of host publication | 2016 IEEE Aerospace Conference, AERO 2016 |
Publisher | IEEE Computer Society |
Volume | 2016-June |
ISBN (Electronic) | 9781467376761 |
DOIs | |
Publication status | Published - 27-06-2016 |
Externally published | Yes |
Event | 2016 IEEE Aerospace Conference, AERO 2016 - Big Sky, United States Duration: 05-03-2016 → 12-03-2016 |
Conference
Conference | 2016 IEEE Aerospace Conference, AERO 2016 |
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Country/Territory | United States |
City | Big Sky |
Period | 05-03-16 → 12-03-16 |
All Science Journal Classification (ASJC) codes
- Aerospace Engineering
- Space and Planetary Science