TY - GEN
T1 - Memory architecture design for nano satellites
AU - Gupta, Nikhil
AU - Shahi, Bhavya
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/6/27
Y1 - 2016/6/27
N2 - This paper describes the memory architecture to improve the data transfer and storage in a small satellite. The main objective during the design stage of the architecture is to find a good balance between power consumption, cost, reliability and data processing capability. These variables directly impact each other, and it is important to achieve a suitable balance. For this, a low power flash memory is selected in conjunction with a faster static random access memory to improve the performance of the on-board computer on the satellite. In-built buffers of flash are suitably used to improve system performance. An extensive study of timing requirements to store data in memory is done. A comparison of performance at different voltage levels above the required minimum is done to get a balance between the required speed of programming the memory and power consumption. A highly modular and optimized algorithm is proposed for data transfer and storage which can be easily incorporated into a real time operating system. A method to further save the power is proposed by switching the flash memory to the power saving mode when its usage is not required.
AB - This paper describes the memory architecture to improve the data transfer and storage in a small satellite. The main objective during the design stage of the architecture is to find a good balance between power consumption, cost, reliability and data processing capability. These variables directly impact each other, and it is important to achieve a suitable balance. For this, a low power flash memory is selected in conjunction with a faster static random access memory to improve the performance of the on-board computer on the satellite. In-built buffers of flash are suitably used to improve system performance. An extensive study of timing requirements to store data in memory is done. A comparison of performance at different voltage levels above the required minimum is done to get a balance between the required speed of programming the memory and power consumption. A highly modular and optimized algorithm is proposed for data transfer and storage which can be easily incorporated into a real time operating system. A method to further save the power is proposed by switching the flash memory to the power saving mode when its usage is not required.
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U2 - 10.1109/AERO.2016.7500695
DO - 10.1109/AERO.2016.7500695
M3 - Conference contribution
AN - SCOPUS:84978532514
VL - 2016-June
T3 - IEEE Aerospace Conference Proceedings
BT - 2016 IEEE Aerospace Conference, AERO 2016
PB - IEEE Computer Society
T2 - 2016 IEEE Aerospace Conference, AERO 2016
Y2 - 5 March 2016 through 12 March 2016
ER -