Memristor augmented ReRAM circuit- a versatile approach

This work presents a novel circuit design that improves the efficiency of data reading in a memristor-augmented ReRAM circuit. The proposed design replaces the standard sense amplifier with a bulk driven transistor for reading the data. The validity of our proposed design has been confirmed by the utilisation of the SPICE Memristor model and CMOS process technology such as 180 nm, 90 nm,45 nm. Hardware implementations on FPGA platforms confirm the effectiveness of the approach under process variation, ensuring reliable deployment in practical settings. In order to enhance the performance of the proposed ReRAM cell, an SSC-MCAM (Store Sense Compare) cell has been developed and tested to confirm its ability to match and not match conditions. Furthermore, a novel CAM architecture has been suggested that eliminates the need for two memristors to store both bit (B) and bitbar (BB). Instead, it only stores bit B and utilises a bulk driven transistor to sense the data. This design allows for the elimination of the match-line Sense Amplifier in our architecture, resulting in a reduction in the number of transistors and ultimately decreasing the die area.