TY - GEN
T1 - Memristor based Adders for High Performance applications
AU - Sri Hari, P.
AU - Ratnakumar, Rahul
AU - Kumar, Om Prakash
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - The memristor is an emerging nanodevice that has recently attracted significant attention from researchers. It combines resistive and memory properties, offering vast potential in nanoelectronics and memory design. A key feature of memristors is their ability to change resistance under voltage control and retain this resistance even after the voltage is removed. Additionally, their small size enables the creation of ultra-compact memory systems. Recognized as the fourth passive circuit element, the memristor offers several advantages, including variable resistance, flexibility, zero leakage current, and compatibility with CMOS technology. In this paper, adder circuits (Half Adder and Full Adder) using both memristors and CMOS within the MRL (Memristor Ratioed Logic) family, utilizing the VTEAM (Voltage Threshold Adaptive Memristor) model has been designed focusing on performance. These circuits are applicable to various logic computing architectures. CMOS transistors are implemented using GPDK 180 nm technology, and parameters such as delay, and power consumption are analyzed. The results show that Memristor based adders can dramatically increase the performance of existing arithmetic circuits empowering the high performance computing arena.
AB - The memristor is an emerging nanodevice that has recently attracted significant attention from researchers. It combines resistive and memory properties, offering vast potential in nanoelectronics and memory design. A key feature of memristors is their ability to change resistance under voltage control and retain this resistance even after the voltage is removed. Additionally, their small size enables the creation of ultra-compact memory systems. Recognized as the fourth passive circuit element, the memristor offers several advantages, including variable resistance, flexibility, zero leakage current, and compatibility with CMOS technology. In this paper, adder circuits (Half Adder and Full Adder) using both memristors and CMOS within the MRL (Memristor Ratioed Logic) family, utilizing the VTEAM (Voltage Threshold Adaptive Memristor) model has been designed focusing on performance. These circuits are applicable to various logic computing architectures. CMOS transistors are implemented using GPDK 180 nm technology, and parameters such as delay, and power consumption are analyzed. The results show that Memristor based adders can dramatically increase the performance of existing arithmetic circuits empowering the high performance computing arena.
UR - https://www.scopus.com/pages/publications/105004556561
UR - https://www.scopus.com/pages/publications/105004556561#tab=citedBy
U2 - 10.1109/AICECS63354.2024.10957584
DO - 10.1109/AICECS63354.2024.10957584
M3 - Conference contribution
AN - SCOPUS:105004556561
T3 - 2024 3rd International Conference on Artificial Intelligence, Computational Electronics and Communication System, AICECS 2024
BT - 2024 3rd International Conference on Artificial Intelligence, Computational Electronics and Communication System, AICECS 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 3rd International Conference on Artificial Intelligence, Computational Electronics and Communication System, AICECS 2024
Y2 - 12 December 2024 through 14 December 2024
ER -