N-Parallel Paths-Based D-Latch for High-Speed Applications

In this paper, a parallel discharge path-based D-latch architecture is proposed to enhance its speed performance compared to the conventional D-latch. The improvement is achieved by incorporating parallel paths at the output node. This increases the effective current at the output node, enabling faster discharge of the load capacitor. The proposed architecture has been designed and extensively simulated using a 180-nm CMOS technology with a supply voltage of 1.8 V. The results demonstrate a decrease in power-delay-product (PDP) by approximately 50.7% compared to the conventional topology. Further, the proposed technique can be extended to any latches.