Nanosheet FET for Future Technology Scaling

Improvements in the VLSI industry have always been striving to justify the Moore’s law by implanting, twice count transistors from the existing one. This law has made a significant improvement in the trends of FET family starting with the straightforward MOSFET with one gate controlling the channel, then next followed by FET with Dual gates, later Tri-gate/Fin FET and now persisting Gate- All-Around Field Effect Transistor. Each era of technology contributed its own advantages and disadvantages. Presently the Gate-All-Around FETs are ruling the FET industry because of its major advantage of improved gate electrostatic integrity over the channel from all the directions, with reduced overall size of the FET. In this research work, the vertically stacked GAA Nanosheet FET is simulated at the device-level using Visual TCAD - 3D Cogenda tool. Research is conducted to substantiate the influence of geometrical variations with respect to thickness and width on the performance of the FET. Parameters analyzed to in the research are ION, IOFF, Switching ratio (ION/IOFF), Subthreshold swing (SS), DIBL, and Threshold voltage (Vth). Device is optimal if it offers better ON current, minimum OFF current. To evaluate this optimal performance the thickness of the nanosheet (NT) is varied from 5 nm to 9 nm, and the width is varied from 10 nm to 50 nm. Visual TCAD - 3D Cogenda tool is used in analyzing the outputs generated and conclude the best geometric dimension for optimum characteristics.