Negative Capacitance Behavior in Cylindrical Ferroelectric-Dielectric Heterostructure

Globally, researchers have been paying close attention to the negative capacitance effect in ferroelectric (FE) materials in the past few years. This phenomenon has the ability to minimize the voltage needed in typical complementary metal-oxide-semiconductor (CMOS) transistors. This study investigates the impact of cylindrical ferroelectric thickness on critical parameters such as negative capacitance stabilization, voltage amplification, and capacitance enhancement within cylindrical heterostructures. Initially, an isolated cylindrical ferroelectric capacitor is analyzed, demonstrating the presence of negative capacitance. Stabilization of this negative capacitance was achieved by integrating a cylindrical dielectric capacitor in line with the ferroelectric capacitor. Our findings show, as the ferroelectric thickness increases, the ferroelectric capacitance decreases and leads to a close capacitance match among the ferroelectric and dielectric capacitors, thereby leading to a significant capacitance enhancement and voltage amplification in the cylindrical heterostructure. Furthermore, the dynamic response for various thicknesses of the cylindrical ferroelectric oxide was also examined, providing comprehensive insights into the behavior of these heterostructures. This study also presents a comparison between planar and cylindrical ferroelectric-dielectric heterostructures, focusing on their performance in voltage amplification. The analysis specifically considers a ferroelectric thickness of 10 nm, highlighting the impact of this particular thickness on the voltage amplification behavior.