Noise Analysis in FinFET-based Analog Circuit with Technology Scaling

Mallikarjun Patil; Rajeewa Kumar Jaisawal; Shashank Banchhor; Navneet Gandhi; Navjeet Bagga; Sunil Rathore; P. N. Kondekar

doi:10.1109/DevIC57758.2023.10134965

Noise Analysis in FinFET-based Analog Circuit with Technology Scaling

Mallikarjun Patil^*
, Rajeewa Kumar Jaisawal
, Shashank Banchhor
, Navneet Gandhi
, Navjeet Bagga
, Sunil Rathore
, P. N. Kondekar

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Noise in any circuit determines the minimum acceptable signal level that can process without compromising its functionality. In field-effect transistors (FETs), mainly two types of noise occur, i.e., flicker (1/1) and thermal noise, which requires proper attention for designing the analog circuits. This paper analyzes the noise behavior in FinFET-based cascode differential amplifier (CDA) for different technological nodes. Using well-calibrated PTM models in HSPICE, we investigated: (i) the Noise behavior in 22nm node FinFET and planarMOSFET; (ii) the impact of FinFET technology nodes (i.e., 16nm, 14nm, 10nm) over noise spectral density; (iii) trend of the corner frequency (f_c) demarcating the flicker and thermal noise in scaled FinFET; (iv) impact of varying the number of fins on the noise behavior. The understanding of Noise in FinFET is thus worth exploring to design reliable FinFET-based analog circuits.

Original language	English
Title of host publication	Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023
Editors	Angsuman Sarkar, Sandip Nandi
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	486-489
Number of pages	4
ISBN (Electronic)	9798350347265
DOIs	https://doi.org/10.1109/DevIC57758.2023.10134965
Publication status	Published - 2023
Event	5th International Conference on Devices for Integrated Circuit, DevIC 2023 - Kalyani, India Duration: 07-04-2023 → 08-04-2023

Publication series

Name	Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023

Conference

Conference	5th International Conference on Devices for Integrated Circuit, DevIC 2023
Country/Territory	India
City	Kalyani
Period	07-04-23 → 08-04-23

All Science Journal Classification (ASJC) codes

Renewable Energy, Sustainability and the Environment
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials
Instrumentation

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/DevIC57758.2023.10134965

Cite this

Patil, M., Jaisawal, R. K., Banchhor, S., Gandhi, N., Bagga, N., Rathore, S., & Kondekar, P. N. (2023). Noise Analysis in FinFET-based Analog Circuit with Technology Scaling. In A. Sarkar, & S. Nandi (Eds.), Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023 (pp. 486-489). (Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DevIC57758.2023.10134965

Patil, Mallikarjun ; Jaisawal, Rajeewa Kumar ; Banchhor, Shashank et al. / Noise Analysis in FinFET-based Analog Circuit with Technology Scaling. Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023. editor / Angsuman Sarkar ; Sandip Nandi. Institute of Electrical and Electronics Engineers Inc., 2023. pp. 486-489 (Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023).

@inproceedings{85facafb457948cd94a2a7f0aff17708,

title = "Noise Analysis in FinFET-based Analog Circuit with Technology Scaling",

abstract = "Noise in any circuit determines the minimum acceptable signal level that can process without compromising its functionality. In field-effect transistors (FETs), mainly two types of noise occur, i.e., flicker (1/1) and thermal noise, which requires proper attention for designing the analog circuits. This paper analyzes the noise behavior in FinFET-based cascode differential amplifier (CDA) for different technological nodes. Using well-calibrated PTM models in HSPICE, we investigated: (i) the Noise behavior in 22nm node FinFET and planarMOSFET; (ii) the impact of FinFET technology nodes (i.e., 16nm, 14nm, 10nm) over noise spectral density; (iii) trend of the corner frequency (f\_c) demarcating the flicker and thermal noise in scaled FinFET; (iv) impact of varying the number of fins on the noise behavior. The understanding of Noise in FinFET is thus worth exploring to design reliable FinFET-based analog circuits.",

author = "Mallikarjun Patil and Jaisawal, \{Rajeewa Kumar\} and Shashank Banchhor and Navneet Gandhi and Navjeet Bagga and Sunil Rathore and Kondekar, \{P. N.\}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 5th International Conference on Devices for Integrated Circuit, DevIC 2023 ; Conference date: 07-04-2023 Through 08-04-2023",

year = "2023",

doi = "10.1109/DevIC57758.2023.10134965",

language = "English",

series = "Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "486--489",

editor = "Angsuman Sarkar and Sandip Nandi",

booktitle = "Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023",

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}

Patil, M, Jaisawal, RK, Banchhor, S, Gandhi, N, Bagga, N, Rathore, S & Kondekar, PN 2023, Noise Analysis in FinFET-based Analog Circuit with Technology Scaling. in A Sarkar & S Nandi (eds), Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023. Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023, Institute of Electrical and Electronics Engineers Inc., pp. 486-489, 5th International Conference on Devices for Integrated Circuit, DevIC 2023, Kalyani, India, 07-04-23. https://doi.org/10.1109/DevIC57758.2023.10134965

Noise Analysis in FinFET-based Analog Circuit with Technology Scaling. / Patil, Mallikarjun; Jaisawal, Rajeewa Kumar; Banchhor, Shashank et al.
Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023. ed. / Angsuman Sarkar; Sandip Nandi. Institute of Electrical and Electronics Engineers Inc., 2023. p. 486-489 (Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Noise Analysis in FinFET-based Analog Circuit with Technology Scaling

AU - Patil, Mallikarjun

AU - Jaisawal, Rajeewa Kumar

AU - Banchhor, Shashank

AU - Gandhi, Navneet

AU - Bagga, Navjeet

AU - Rathore, Sunil

AU - Kondekar, P. N.

PY - 2023

Y1 - 2023

N2 - Noise in any circuit determines the minimum acceptable signal level that can process without compromising its functionality. In field-effect transistors (FETs), mainly two types of noise occur, i.e., flicker (1/1) and thermal noise, which requires proper attention for designing the analog circuits. This paper analyzes the noise behavior in FinFET-based cascode differential amplifier (CDA) for different technological nodes. Using well-calibrated PTM models in HSPICE, we investigated: (i) the Noise behavior in 22nm node FinFET and planarMOSFET; (ii) the impact of FinFET technology nodes (i.e., 16nm, 14nm, 10nm) over noise spectral density; (iii) trend of the corner frequency (f_c) demarcating the flicker and thermal noise in scaled FinFET; (iv) impact of varying the number of fins on the noise behavior. The understanding of Noise in FinFET is thus worth exploring to design reliable FinFET-based analog circuits.

AB - Noise in any circuit determines the minimum acceptable signal level that can process without compromising its functionality. In field-effect transistors (FETs), mainly two types of noise occur, i.e., flicker (1/1) and thermal noise, which requires proper attention for designing the analog circuits. This paper analyzes the noise behavior in FinFET-based cascode differential amplifier (CDA) for different technological nodes. Using well-calibrated PTM models in HSPICE, we investigated: (i) the Noise behavior in 22nm node FinFET and planarMOSFET; (ii) the impact of FinFET technology nodes (i.e., 16nm, 14nm, 10nm) over noise spectral density; (iii) trend of the corner frequency (f_c) demarcating the flicker and thermal noise in scaled FinFET; (iv) impact of varying the number of fins on the noise behavior. The understanding of Noise in FinFET is thus worth exploring to design reliable FinFET-based analog circuits.

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M3 - Conference contribution

AN - SCOPUS:85162090531

T3 - Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023

SP - 486

EP - 489

BT - Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023

A2 - Sarkar, Angsuman

A2 - Nandi, Sandip

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 5th International Conference on Devices for Integrated Circuit, DevIC 2023

Y2 - 7 April 2023 through 8 April 2023

ER -

Patil M, Jaisawal RK, Banchhor S, Gandhi N, Bagga N, Rathore S et al. Noise Analysis in FinFET-based Analog Circuit with Technology Scaling. In Sarkar A, Nandi S, editors, Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023. Institute of Electrical and Electronics Engineers Inc. 2023. p. 486-489. (Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023). doi: 10.1109/DevIC57758.2023.10134965

Noise Analysis in FinFET-based Analog Circuit with Technology Scaling

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