Novel method of digital clock frequency multiplication and division using floating point arithmetic

Sundaresan Chidambaram; Vishnu Satya Chaitanya

doi:10.1109/ISMS.2013.22

Novel method of digital clock frequency multiplication and division using floating point arithmetic

Sundaresan Chidambaram, Vishnu Satya Chaitanya

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A digital clock frequency multiplier, divisor using floating point arithmetic which generates the output clock with almost zero frequency error has been presented. The circuit has an unbounded multiplication and division factor range and low lock time. A low power mechanism has been incorporated to ensure that the overall power consumption of the circuit is less. The circuit has been designed in TSMC 65nm CMOS process for an input reference time of 0.01ns and has been verified with random multiplication factor values.

Original language	English
Title of host publication	Proceedings - 4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013
Pages	592-595
Number of pages	4
DOIs	https://doi.org/10.1109/ISMS.2013.22
Publication status	Published - 20-05-2013
Event	4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013 - Bangkok, Thailand Duration: 29-01-2013 → 31-01-2013

Conference

Conference	4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013
Country/Territory	Thailand
City	Bangkok
Period	29-01-13 → 31-01-13

All Science Journal Classification (ASJC) codes

Artificial Intelligence
Software
Modelling and Simulation
Theoretical Computer Science

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10.1109/ISMS.2013.22

Cite this

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title = "Novel method of digital clock frequency multiplication and division using floating point arithmetic",

abstract = "A digital clock frequency multiplier, divisor using floating point arithmetic which generates the output clock with almost zero frequency error has been presented. The circuit has an unbounded multiplication and division factor range and low lock time. A low power mechanism has been incorporated to ensure that the overall power consumption of the circuit is less. The circuit has been designed in TSMC 65nm CMOS process for an input reference time of 0.01ns and has been verified with random multiplication factor values.",

author = "Sundaresan Chidambaram and Chaitanya, {Vishnu Satya}",

year = "2013",

month = may,

day = "20",

doi = "10.1109/ISMS.2013.22",

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pages = "592--595",

booktitle = "Proceedings - 4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013",

note = "4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013 ; Conference date: 29-01-2013 Through 31-01-2013",

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Chidambaram, S & Chaitanya, VS 2013, Novel method of digital clock frequency multiplication and division using floating point arithmetic. in Proceedings - 4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013., 6498340, pp. 592-595, 4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013, Bangkok, Thailand, 29-01-13. https://doi.org/10.1109/ISMS.2013.22

Novel method of digital clock frequency multiplication and division using floating point arithmetic. / Chidambaram, Sundaresan; Chaitanya, Vishnu Satya.
Proceedings - 4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013. 2013. p. 592-595 6498340.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - A digital clock frequency multiplier, divisor using floating point arithmetic which generates the output clock with almost zero frequency error has been presented. The circuit has an unbounded multiplication and division factor range and low lock time. A low power mechanism has been incorporated to ensure that the overall power consumption of the circuit is less. The circuit has been designed in TSMC 65nm CMOS process for an input reference time of 0.01ns and has been verified with random multiplication factor values.

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ER -

Novel method of digital clock frequency multiplication and division using floating point arithmetic

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