Performance Analysis of 64×64 bit Multiplier Designed Using Urdhva Tiryakbyham and Nikhilam Navatashcaramam Dashatah Sutras

In VLSI systems like microprocessors and application specific DSP architectures, the arithmetic operation which is extensively used is 'Multiplication'. The overall performance of most of the systems is determined by the multipliers. The power efficient, faster and low area multiplier design decides the performance of the system. This paper focuses on the comparison of the 64×64 bit multipliers based on the Urdhva Tiryakbyham and Nikhilam Navatashcaramam Dashatah sutras of Vedic mathematics. The proposed designs were implemented using Verilog code and simulated using Xilinx10.1 for parameters such as slices, number of 4 input LUT's and delay. Simulation was also done using Cadence simvision with 45nm technology. 64×64 bit multiplier designed using Urdhva Tiryakbyham sutra exhibits less combinational delay and power utilization. But device utilization in Nikhilam multiplication is less compared to Urdhva multiplication.