Performance Analysis of an Energy Efficient 1-Bit Hybrid Full Adder

This paper presents the design and analysis of hybrid adders utilizing transmission gate, CMOS logic, and pass transistor logic. In this work, simulation is conducted using 45nm technology. The adder architecture comprises three main modules: XOR, sum, and carry. The XOR module employs transmission gate logic and CMOS logic, while the sum module integrates transmission gate logic and XOR/XNOR operations. The carry module is built using pass transistor logic. An in-depth analysis was conducted on the designed hybrid adder circuit, with meticulous measurements and evaluations of its power consumption, delay, and power-delay product (PDP) to provide comprehensive insights into its performance and efficiency. The results demonstrate the effectiveness of the hybrid adder architecture in meeting the demands of modern digital systems while leveraging the benefits of advanced semiconductor manufacturing processes.