Performance analysis of mixed logic decoders using cylindrical FinFET technology at 22 nm node

This paper presents a comparative performance evaluation of mixed logic decoders—2-to-4 and 4-to-16—implemented using traditional Metal-Oxide-Semiconductor (MOS) and advanced cylindrical FinFET technologies at the 22 nm scale. Simulation Program with Integrated Circuit Emphasis (HSPICE) simulations were conducted using the BSIM-CMG model, and results were validated through transient analysis on Avanwaves. The designs utilize both 14T and 15T transistor architectures. Experimental results show that cylindrical FinFET-based decoders significantly outperform their MOS counterparts in terms of average power consumption, power-delay product (PDP), and power dissipation. The Cylindrical FinFET 2:4 decoder achieved over 99.5% reduction in power consumption and PDP compared to the MOS-based implementation. Similar improvements were observed for 4:16 decoders, validating the FinFET’s efficiency in low-power high-performance digital design. The study supports the integration of FinFET devices for future scalable decoder architectures with superior energy efficiency.