Performance Evaluation of STT and SOT MTJ-Based Majority Gate Designs for In-Memory Computing

In-memory computing (IMC) has emerged as a promising paradigm to address the energy and latency bottlenecks posed by traditional von Neumann architectures. Majority logic, due to its simplicity and expressive power, is particularly suited for arithmetic-intensive applications within IMC systems. This work presents a comparative implementation and analysis of a 3-input non-volatile magnetic majority gate (NVMAG) using two magnetic tunnel junction (MTJ) technologies: Spin-Transfer Torque (STT) and Voltage-Gated Spin-Orbit Torque (VGSOT). STT-MRAM, although widely adopted, suffers from high write energy and read disturbance. Alternatively, the VGSOT-MTJ, leveraging spin Hall effect-based switching and voltage control of magnetic anisotropy (VCMA), offers a low-power, field-free solution with enhanced stability and reduced energy requirements. The study explores both parallel and cascaded configurations of differential memory cells based on these MTJs to evaluate their impact on energy efficiency, latency, and sense margin. Results demonstrate that VGSOT-MTJ-based designs significantly outperform their STT counterparts, achieving up to 97.6% energy savings and 86.5% latency reduction. Furthermore, parallel configurations of VGSOT-MTJs offer enhanced performance over series arrangements. These findings validate the advantages of VGSOT-MTJ technology for next-generation, ultra-low-power IMC systems, emphasizing its potential to enable scalable, high-performance majority logic computation within memory arrays.