Probabilistic power analysis technique for low power VLSI circuits

Here i have reviewed the previous works in literature for low power at gate level logic transformation in synthesis process. I applied the probabilistic power analysis technique with an example f = b(a+c) and same is proved using MATLAB 7.10.0 (R2010a). I showed the advantage of Binary Decision Diagram (BDD) for computing the probability of given Boolean function. The effect of technology mapping is reviewed with an example f = ab + cd using the cost metric of minimum area and minimum power mapping. The area mapped circuit has less area than the power mapped circuit but it has 22% higher switched capacitance as reported in literature. I observed that the area mapped circuit has ≈ 28 % less area and power cost has also been reduced three times of power mapped circuit for the same circuit with probability P (a, b, c = 1) = 0.5. The reason for this effective change is the transition probability (P_t). I found that in minimum area mapping the lower transition probability (P_t = 0.058) point is driven by AOI22 library having high intrinsic and load capacitance while in minimum power mapping case the lower transition probability point is driven by a much lower capacitance of G3, a NAND2 gate. Beside that internal switching capacitance of G1 and G2 is included to make the power cost so high. I also showed that a tree structure consume more power than a chain structure with an example f = abcd, the same is used to show the effect of pin ordering on transition probabilities that directly affect the dynamic power.