RTL to GDSII Implementation of RADIX-4 Booth Multiplier using Opensource EDA tools

Rishabh Jain; Shounak De; K. G. Shreeharsha

doi:10.1109/CCPIS59145.2023.10291665

RTL to GDSII Implementation of RADIX-4 Booth Multiplier using Opensource EDA tools

Rishabh Jain^*
, Shounak De
, K. G. Shreeharsha

^*Corresponding author for this work

Manipal Institute of Technology, Manipal

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper aims to presents a fast, low power and optimum chip area architecture for Radix-4, 8-bit booth multiplier. Skywater 130nm CMOS technology node is used to achieve the desired Circuit synthesis and post-layout simulation. RTL to GDSII workflow is implemented by utilising open-source EDA tools from the Openlane framework. The proposed circuit implementation occupies an area of 16457.830 and consumes 494uW at 66.67 MHz. In comparison to existing 8-bit multiplier implementation, the proposed multiplier architecture is 33% faster and 11% lower power consumption. It also aims to demonstrate the capability of opensource EDA environment and the further advancement in opensource ASIC IP design.

Original language	English
Title of host publication	2023 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350315769
DOIs	https://doi.org/10.1109/CCPIS59145.2023.10291665
Publication status	Published - 2023
Event	1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023 - Bhubaneswar, India Duration: 01-09-2023 → 03-09-2023

Publication series

Name	2023 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023

Conference

Conference	1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023
Country/Territory	India
City	Bhubaneswar
Period	01-09-23 → 03-09-23

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Renewable Energy, Sustainability and the Environment
Electrical and Electronic Engineering
Control and Optimization
Artificial Intelligence
Computer Vision and Pattern Recognition
Information Systems and Management
Energy Engineering and Power Technology

Access to Document

10.1109/CCPIS59145.2023.10291665

Cite this

Jain, R., De, S., & Shreeharsha, K. G. (2023). RTL to GDSII Implementation of RADIX-4 Booth Multiplier using Opensource EDA tools. In 2023 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023 (2023 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CCPIS59145.2023.10291665

Jain, Rishabh ; De, Shounak ; Shreeharsha, K. G. / RTL to GDSII Implementation of RADIX-4 Booth Multiplier using Opensource EDA tools. 2023 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023).

@inproceedings{9dd4447bbb9d4f059885e34d786626be,

title = "RTL to GDSII Implementation of RADIX-4 Booth Multiplier using Opensource EDA tools",

abstract = "This paper aims to presents a fast, low power and optimum chip area architecture for Radix-4, 8-bit booth multiplier. Skywater 130nm CMOS technology node is used to achieve the desired Circuit synthesis and post-layout simulation. RTL to GDSII workflow is implemented by utilising open-source EDA tools from the Openlane framework. The proposed circuit implementation occupies an area of 16457.830 and consumes 494uW at 66.67 MHz. In comparison to existing 8-bit multiplier implementation, the proposed multiplier architecture is 33\% faster and 11\% lower power consumption. It also aims to demonstrate the capability of opensource EDA environment and the further advancement in opensource ASIC IP design.",

author = "Rishabh Jain and Shounak De and Shreeharsha, \{K. G.\}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023 ; Conference date: 01-09-2023 Through 03-09-2023",

year = "2023",

doi = "10.1109/CCPIS59145.2023.10291665",

language = "English",

series = "2023 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023",

address = "United States",

}

Jain, R, De, S & Shreeharsha, KG 2023, RTL to GDSII Implementation of RADIX-4 Booth Multiplier using Opensource EDA tools. in 2023 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023. 2023 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023, Institute of Electrical and Electronics Engineers Inc., 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023, Bhubaneswar, India, 01-09-23. https://doi.org/10.1109/CCPIS59145.2023.10291665

RTL to GDSII Implementation of RADIX-4 Booth Multiplier using Opensource EDA tools. / Jain, Rishabh; De, Shounak ; Shreeharsha, K. G.
2023 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - RTL to GDSII Implementation of RADIX-4 Booth Multiplier using Opensource EDA tools

AU - Jain, Rishabh

AU - De, Shounak

AU - Shreeharsha, K. G.

PY - 2023

Y1 - 2023

N2 - This paper aims to presents a fast, low power and optimum chip area architecture for Radix-4, 8-bit booth multiplier. Skywater 130nm CMOS technology node is used to achieve the desired Circuit synthesis and post-layout simulation. RTL to GDSII workflow is implemented by utilising open-source EDA tools from the Openlane framework. The proposed circuit implementation occupies an area of 16457.830 and consumes 494uW at 66.67 MHz. In comparison to existing 8-bit multiplier implementation, the proposed multiplier architecture is 33% faster and 11% lower power consumption. It also aims to demonstrate the capability of opensource EDA environment and the further advancement in opensource ASIC IP design.

AB - This paper aims to presents a fast, low power and optimum chip area architecture for Radix-4, 8-bit booth multiplier. Skywater 130nm CMOS technology node is used to achieve the desired Circuit synthesis and post-layout simulation. RTL to GDSII workflow is implemented by utilising open-source EDA tools from the Openlane framework. The proposed circuit implementation occupies an area of 16457.830 and consumes 494uW at 66.67 MHz. In comparison to existing 8-bit multiplier implementation, the proposed multiplier architecture is 33% faster and 11% lower power consumption. It also aims to demonstrate the capability of opensource EDA environment and the further advancement in opensource ASIC IP design.

UR - https://www.scopus.com/pages/publications/85177556081

UR - https://www.scopus.com/pages/publications/85177556081#tab=citedBy

U2 - 10.1109/CCPIS59145.2023.10291665

DO - 10.1109/CCPIS59145.2023.10291665

M3 - Conference contribution

AN - SCOPUS:85177556081

T3 - 2023 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023

BT - 2023 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023

Y2 - 1 September 2023 through 3 September 2023

ER -

Jain R, De S , Shreeharsha KG. RTL to GDSII Implementation of RADIX-4 Booth Multiplier using Opensource EDA tools. In 2023 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (2023 1st International Conference on Circuits, Power, and Intelligent Systems, CCPIS 2023). doi: 10.1109/CCPIS59145.2023.10291665

RTL to GDSII Implementation of RADIX-4 Booth Multiplier using Opensource EDA tools

Abstract

Publication series

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UN SDGs

All Science Journal Classification (ASJC) codes

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