TY - GEN
T1 - Self-heating and Process Induced Performance Barrier on Complementary Field Effect Transistor
T2 - 9th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2025
AU - Kumar, Sandeep
AU - Patil, Deven H.
AU - Jain, Khushi
AU - Dixit, Ankit
AU - Rathore, Sunil
AU - Shakir, Mohd
AU - Kumar, Naveen
AU - Georgiev, Vihar
AU - Dasgupta, S.
AU - Bagga, Navjeet
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - The vertical nanosheet (channels) stacking and aligned in such a way that nFET is kept over pFET, or vice-versa, raises severe reliability concerns in Complementary FET (CFET). In this paper, using well-calibrated TCAD models, all the related reliability issues are being analyzed, such as: (i) the role of dielectric separation wall (DSW) in electrical and thermal cross-talk from nFET to pFET and vice-versa; (ii) the impact of self-heating effect (SHE) on self- and the other side of the DSW; (iii) impact of random dopant fluctuations (RDF) on threshold voltage (Vth); (iv) impact of line-edge roughness (LER) on ION and Vth; (v) effect of metal grain granularities (MGG) and the ratio of grain size to gate area (RGG) on device merits, viz ION and Vth; and finally (vi) the device aging is predicated using the 8shift in Vth9 by ±50mV. Thus, the proposed analysis benchmarks a reliable CFET design.
AB - The vertical nanosheet (channels) stacking and aligned in such a way that nFET is kept over pFET, or vice-versa, raises severe reliability concerns in Complementary FET (CFET). In this paper, using well-calibrated TCAD models, all the related reliability issues are being analyzed, such as: (i) the role of dielectric separation wall (DSW) in electrical and thermal cross-talk from nFET to pFET and vice-versa; (ii) the impact of self-heating effect (SHE) on self- and the other side of the DSW; (iii) impact of random dopant fluctuations (RDF) on threshold voltage (Vth); (iv) impact of line-edge roughness (LER) on ION and Vth; (v) effect of metal grain granularities (MGG) and the ratio of grain size to gate area (RGG) on device merits, viz ION and Vth; and finally (vi) the device aging is predicated using the 8shift in Vth9 by ±50mV. Thus, the proposed analysis benchmarks a reliable CFET design.
UR - https://www.scopus.com/pages/publications/105010830797
UR - https://www.scopus.com/pages/publications/105010830797#tab=citedBy
U2 - 10.1109/EDTM61175.2025.11041030
DO - 10.1109/EDTM61175.2025.11041030
M3 - Conference contribution
AN - SCOPUS:105010830797
T3 - 9th IEEE Electron Devices Technology and Manufacturing Conference: Shaping the Future with Innovations in Devices and Manufacturing, EDTM 2025
BT - 9th IEEE Electron Devices Technology and Manufacturing Conference
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 9 March 2025 through 12 March 2025
ER -