Self-Heating Induced Differential Resistance in Complementary FET: The Role of Dielectric Insulation in Thermal Dynamics

The heat flux confined within the sheets or channels, i.e., between the gate dielectric and across the dielectric sidewall (D_SW), engenders a severe self-heating effect (SHE) in stacked transistors like Complementary FETs (CFETs). This heat accumulation due to SHE reduces the velocity and mobility of charge carriers in the channel region, resulting in the negative differential resistance (NDR). This paper extensively provides insight into SHE in CFETs using a first-principles approach, i.e., from the fundamental current equation. In a conventional case, the carrier mobility, carrier concentration, velocity, and threshold voltage are temperature-dependent parameters; however, with SHE, the current (I_DS) is also drain-voltage (V_DS) dependent. Using well-calibrated TCAD models, we demonstrate the electrical and thermal characteristics of the CFET by extracting the I_DS gradient as a function of temperature. We also investigated the CFET performance of the device under various parametric conditions, including channel width (W_CH), channel thickness (T_CH), and extension length (L_EXT), and explained the significance of the dielectric layer in heat coupling across the D_SW. The design guidelines for optimal W_CH, T_CH, and L_EXT are presented, considering I_ON/C_gg and intrinsic RC delay, as figure-of-merits. Henceforth, the proposed work underscores the importance of integrated electrical and thermal evaluations in establishing a robust framework for reliable and energy-efficient CFET architectures.