TY - GEN
T1 - Seven-Level Single-Phase Reduced Device Count Multilevel Inverter
AU - Patel, Dilip Kumar
AU - Dewangan, Niraj Kumar
AU - Kumar, Dhananjay
AU - Rathore, Arun
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - In this article, a new single-phase multilevel inverter is presented, one with reduced device count and less voltage stress on the power switches. Seven voltage levels are produced using this design in an asymmetrical voltage source setup. Two input dc sources and six semiconductor switches make up the proposed configuration. Complexity, cost, size, and performance were all improved by reducing power switches, DC voltage, and driving circuits. The elimination of switches, DC voltage, and driving circuits reduced complexity, size, and cost along with increased efficiency. The proposed architecture can be used for applications involving industrial drives as well as R and RL loads. Comparisons are made between traditional and proposed topology based on power switch ratio, DC source, and other variables. Utilizing MATLAB/SIMULINK, the proposed asymmetrical multilevel structure is validated.
AB - In this article, a new single-phase multilevel inverter is presented, one with reduced device count and less voltage stress on the power switches. Seven voltage levels are produced using this design in an asymmetrical voltage source setup. Two input dc sources and six semiconductor switches make up the proposed configuration. Complexity, cost, size, and performance were all improved by reducing power switches, DC voltage, and driving circuits. The elimination of switches, DC voltage, and driving circuits reduced complexity, size, and cost along with increased efficiency. The proposed architecture can be used for applications involving industrial drives as well as R and RL loads. Comparisons are made between traditional and proposed topology based on power switch ratio, DC source, and other variables. Utilizing MATLAB/SIMULINK, the proposed asymmetrical multilevel structure is validated.
UR - http://www.scopus.com/inward/record.url?scp=85151529080&partnerID=8YFLogxK
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U2 - 10.1109/SCEECS57921.2023.10063035
DO - 10.1109/SCEECS57921.2023.10063035
M3 - Conference contribution
AN - SCOPUS:85151529080
T3 - 2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023
BT - 2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023
Y2 - 18 February 2023 through 19 February 2023
ER -
