Seven-Level Single-Phase Reduced Device Count Multilevel Inverter

Dilip Kumar Patel; Niraj Kumar Dewangan; Dhananjay Kumar; Arun Rathore

doi:10.1109/SCEECS57921.2023.10063035

Seven-Level Single-Phase Reduced Device Count Multilevel Inverter

Dilip Kumar Patel
, Niraj Kumar Dewangan
, Dhananjay Kumar
, Arun Rathore

Manipal Institute of Technology, Manipal

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

In this article, a new single-phase multilevel inverter is presented, one with reduced device count and less voltage stress on the power switches. Seven voltage levels are produced using this design in an asymmetrical voltage source setup. Two input dc sources and six semiconductor switches make up the proposed configuration. Complexity, cost, size, and performance were all improved by reducing power switches, DC voltage, and driving circuits. The elimination of switches, DC voltage, and driving circuits reduced complexity, size, and cost along with increased efficiency. The proposed architecture can be used for applications involving industrial drives as well as R and RL loads. Comparisons are made between traditional and proposed topology based on power switch ratio, DC source, and other variables. Utilizing MATLAB/SIMULINK, the proposed asymmetrical multilevel structure is validated.

Original language	English
Title of host publication	2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350398748
DOIs	https://doi.org/10.1109/SCEECS57921.2023.10063035
Publication status	Published - 2023
Event	2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023 - Bhopal, India Duration: 18-02-2023 → 19-02-2023

Publication series

Name	2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023

Conference

Conference	2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023
Country/Territory	India
City	Bhopal
Period	18-02-23 → 19-02-23

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Artificial Intelligence
Computer Science Applications
Information Systems
Information Systems and Management
Energy Engineering and Power Technology
Renewable Energy, Sustainability and the Environment
Electrical and Electronic Engineering

Access to Document

10.1109/SCEECS57921.2023.10063035

Cite this

Patel, D. K., Dewangan, N. K., Kumar, D., & Rathore, A. (2023). Seven-Level Single-Phase Reduced Device Count Multilevel Inverter. In 2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023 (2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SCEECS57921.2023.10063035

Patel, Dilip Kumar ; Dewangan, Niraj Kumar ; Kumar, Dhananjay et al. / Seven-Level Single-Phase Reduced Device Count Multilevel Inverter. 2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023).

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title = "Seven-Level Single-Phase Reduced Device Count Multilevel Inverter",

abstract = "In this article, a new single-phase multilevel inverter is presented, one with reduced device count and less voltage stress on the power switches. Seven voltage levels are produced using this design in an asymmetrical voltage source setup. Two input dc sources and six semiconductor switches make up the proposed configuration. Complexity, cost, size, and performance were all improved by reducing power switches, DC voltage, and driving circuits. The elimination of switches, DC voltage, and driving circuits reduced complexity, size, and cost along with increased efficiency. The proposed architecture can be used for applications involving industrial drives as well as R and RL loads. Comparisons are made between traditional and proposed topology based on power switch ratio, DC source, and other variables. Utilizing MATLAB/SIMULINK, the proposed asymmetrical multilevel structure is validated.",

author = "Patel, \{Dilip Kumar\} and Dewangan, \{Niraj Kumar\} and Dhananjay Kumar and Arun Rathore",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023 ; Conference date: 18-02-2023 Through 19-02-2023",

year = "2023",

doi = "10.1109/SCEECS57921.2023.10063035",

language = "English",

series = "2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023",

address = "United States",

}

Patel, DK, Dewangan, NK, Kumar, D & Rathore, A 2023, Seven-Level Single-Phase Reduced Device Count Multilevel Inverter. in 2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023. 2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023, Institute of Electrical and Electronics Engineers Inc., 2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023, Bhopal, India, 18-02-23. https://doi.org/10.1109/SCEECS57921.2023.10063035

Seven-Level Single-Phase Reduced Device Count Multilevel Inverter. / Patel, Dilip Kumar; Dewangan, Niraj Kumar; Kumar, Dhananjay et al.
2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Seven-Level Single-Phase Reduced Device Count Multilevel Inverter

AU - Patel, Dilip Kumar

AU - Dewangan, Niraj Kumar

AU - Kumar, Dhananjay

AU - Rathore, Arun

PY - 2023

Y1 - 2023

N2 - In this article, a new single-phase multilevel inverter is presented, one with reduced device count and less voltage stress on the power switches. Seven voltage levels are produced using this design in an asymmetrical voltage source setup. Two input dc sources and six semiconductor switches make up the proposed configuration. Complexity, cost, size, and performance were all improved by reducing power switches, DC voltage, and driving circuits. The elimination of switches, DC voltage, and driving circuits reduced complexity, size, and cost along with increased efficiency. The proposed architecture can be used for applications involving industrial drives as well as R and RL loads. Comparisons are made between traditional and proposed topology based on power switch ratio, DC source, and other variables. Utilizing MATLAB/SIMULINK, the proposed asymmetrical multilevel structure is validated.

AB - In this article, a new single-phase multilevel inverter is presented, one with reduced device count and less voltage stress on the power switches. Seven voltage levels are produced using this design in an asymmetrical voltage source setup. Two input dc sources and six semiconductor switches make up the proposed configuration. Complexity, cost, size, and performance were all improved by reducing power switches, DC voltage, and driving circuits. The elimination of switches, DC voltage, and driving circuits reduced complexity, size, and cost along with increased efficiency. The proposed architecture can be used for applications involving industrial drives as well as R and RL loads. Comparisons are made between traditional and proposed topology based on power switch ratio, DC source, and other variables. Utilizing MATLAB/SIMULINK, the proposed asymmetrical multilevel structure is validated.

UR - https://www.scopus.com/pages/publications/85151529080

UR - https://www.scopus.com/pages/publications/85151529080#tab=citedBy

U2 - 10.1109/SCEECS57921.2023.10063035

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M3 - Conference contribution

AN - SCOPUS:85151529080

T3 - 2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023

BT - 2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023

Y2 - 18 February 2023 through 19 February 2023

ER -

Patel DK, Dewangan NK, Kumar D, Rathore A. Seven-Level Single-Phase Reduced Device Count Multilevel Inverter. In 2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2023). doi: 10.1109/SCEECS57921.2023.10063035

Seven-Level Single-Phase Reduced Device Count Multilevel Inverter

Abstract

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UN SDGs

All Science Journal Classification (ASJC) codes

Access to Document

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