SO-OTA Based Emulator Circuit for Extended Memristor with Hysteresis Loop of Type II

V. Raghavendra; D. V. Kamath

doi:10.1109/ICESC48915.2020.9155689

SO-OTA Based Emulator Circuit for Extended Memristor with Hysteresis Loop of Type II

V. Raghavendra, D. V. Kamath

Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents an emulator circuit using single-output operational transconductance amplifier (SO-OTA) for an extended memristor which provides a hysteretic loop of type II. The type I 'pinched hysteresis' curve of the memristor usually traces in the I and III quadrant of I- V plane in anticlockwise-clockwise or clockwise-anticlockwise direction. The hysteresis curve of proposed extended memristor emulator circuit traces in the anticlockwise-anticlockwise direction in first and third quadrants of I-V plane. The Cadence simulation results are provided for design verification.

Original language	English
Title of host publication	Proceedings of the International Conference on Electronics and Sustainable Communication Systems, ICESC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	984-988
Number of pages	5
ISBN (Electronic)	9781728141084
DOIs	https://doi.org/10.1109/ICESC48915.2020.9155689
Publication status	Published - 07-2020
Event	2020 International Conference on Electronics and Sustainable Communication Systems, ICESC 2020 - Coimbatore, India Duration: 02-07-2020 → 04-07-2020

Publication series

Name	Proceedings of the International Conference on Electronics and Sustainable Communication Systems, ICESC 2020

Conference

Conference	2020 International Conference on Electronics and Sustainable Communication Systems, ICESC 2020
Country/Territory	India
City	Coimbatore
Period	02-07-20 → 04-07-20

All Science Journal Classification (ASJC) codes

Artificial Intelligence
Computer Networks and Communications
Information Systems and Management
Renewable Energy, Sustainability and the Environment
Safety, Risk, Reliability and Quality
Instrumentation
Communication

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ICESC48915.2020.9155689

Cite this

Raghavendra, V., & Kamath, D. V. (2020). SO-OTA Based Emulator Circuit for Extended Memristor with Hysteresis Loop of Type II. In Proceedings of the International Conference on Electronics and Sustainable Communication Systems, ICESC 2020 (pp. 984-988). Article 9155689 (Proceedings of the International Conference on Electronics and Sustainable Communication Systems, ICESC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICESC48915.2020.9155689

Raghavendra, V. ; Kamath, D. V. / SO-OTA Based Emulator Circuit for Extended Memristor with Hysteresis Loop of Type II. Proceedings of the International Conference on Electronics and Sustainable Communication Systems, ICESC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 984-988 (Proceedings of the International Conference on Electronics and Sustainable Communication Systems, ICESC 2020).

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title = "SO-OTA Based Emulator Circuit for Extended Memristor with Hysteresis Loop of Type II",

abstract = "This paper presents an emulator circuit using single-output operational transconductance amplifier (SO-OTA) for an extended memristor which provides a hysteretic loop of type II. The type I 'pinched hysteresis' curve of the memristor usually traces in the I and III quadrant of I- V plane in anticlockwise-clockwise or clockwise-anticlockwise direction. The hysteresis curve of proposed extended memristor emulator circuit traces in the anticlockwise-anticlockwise direction in first and third quadrants of I-V plane. The Cadence simulation results are provided for design verification.",

author = "V. Raghavendra and Kamath, \{D. V.\}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 International Conference on Electronics and Sustainable Communication Systems, ICESC 2020 ; Conference date: 02-07-2020 Through 04-07-2020",

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Raghavendra, V & Kamath, DV 2020, SO-OTA Based Emulator Circuit for Extended Memristor with Hysteresis Loop of Type II. in Proceedings of the International Conference on Electronics and Sustainable Communication Systems, ICESC 2020., 9155689, Proceedings of the International Conference on Electronics and Sustainable Communication Systems, ICESC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 984-988, 2020 International Conference on Electronics and Sustainable Communication Systems, ICESC 2020, Coimbatore, India, 02-07-20. https://doi.org/10.1109/ICESC48915.2020.9155689

SO-OTA Based Emulator Circuit for Extended Memristor with Hysteresis Loop of Type II. / Raghavendra, V.; Kamath, D. V.
Proceedings of the International Conference on Electronics and Sustainable Communication Systems, ICESC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 984-988 9155689 (Proceedings of the International Conference on Electronics and Sustainable Communication Systems, ICESC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

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AU - Kamath, D. V.

PY - 2020/7

Y1 - 2020/7

N2 - This paper presents an emulator circuit using single-output operational transconductance amplifier (SO-OTA) for an extended memristor which provides a hysteretic loop of type II. The type I 'pinched hysteresis' curve of the memristor usually traces in the I and III quadrant of I- V plane in anticlockwise-clockwise or clockwise-anticlockwise direction. The hysteresis curve of proposed extended memristor emulator circuit traces in the anticlockwise-anticlockwise direction in first and third quadrants of I-V plane. The Cadence simulation results are provided for design verification.

AB - This paper presents an emulator circuit using single-output operational transconductance amplifier (SO-OTA) for an extended memristor which provides a hysteretic loop of type II. The type I 'pinched hysteresis' curve of the memristor usually traces in the I and III quadrant of I- V plane in anticlockwise-clockwise or clockwise-anticlockwise direction. The hysteresis curve of proposed extended memristor emulator circuit traces in the anticlockwise-anticlockwise direction in first and third quadrants of I-V plane. The Cadence simulation results are provided for design verification.

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DO - 10.1109/ICESC48915.2020.9155689

M3 - Conference contribution

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T3 - Proceedings of the International Conference on Electronics and Sustainable Communication Systems, ICESC 2020

SP - 984

EP - 988

BT - Proceedings of the International Conference on Electronics and Sustainable Communication Systems, ICESC 2020

PB - Institute of Electrical and Electronics Engineers Inc.

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Y2 - 2 July 2020 through 4 July 2020

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Raghavendra V, Kamath DV. SO-OTA Based Emulator Circuit for Extended Memristor with Hysteresis Loop of Type II. In Proceedings of the International Conference on Electronics and Sustainable Communication Systems, ICESC 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 984-988. 9155689. (Proceedings of the International Conference on Electronics and Sustainable Communication Systems, ICESC 2020). doi: 10.1109/ICESC48915.2020.9155689

SO-OTA Based Emulator Circuit for Extended Memristor with Hysteresis Loop of Type II

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