TY - GEN
T1 - Statistical Analysis of Metal Grain Granularities Induced Variability in 4T Complementary FET SRAM Cell
AU - Patil, Deven H.
AU - Kumar, Sandeep
AU - Rathore, Sunil
AU - Dasgupta, S.
AU - Bagga, Navjeet
N1 - Publisher Copyright:
© 2026 IEEE.
PY - 2026
Y1 - 2026
N2 - Complementary FETs (CFETs) vertically stack n- and p-FETs to achieve superior scaling; however, the confined gate metal thickness induces Metal Grain Granularity (MGG)-related workfunction fluctuations. Using well-calibrated TCAD simulations, this proposed study investigates: (i) the impact of MGG on threshold voltage deviation (σVth), (ii) its influence on the static behavior of a 1T CFET inverter, and (iii) the resulting variability in the static noise margin (SNM) of a 4T CFET SRAM cell. The random grain orientations and boundaries yield σVth of ~10 mV (nFET) and ~9 mV (pFET), resulting in a ±13.2 mV shift in inverter switching threshold (VM) for a 2 nm average grain size (Gr). Consequently, MGG-induced variability significantly degrades SRAM stability, with σSNM rising from 5 mV to 26.3 mV (Read) and from 8.3 mV to 39.7 mV (Hold) when Gr varied from 2 to 8nm. This indicates enhanced variability from reduced boundary averaging, with the Hold state showing greater deviation due to node isolation and positive feedback effects. Furthermore, histograms, QQ plots, and correlation plots have been used to determine the symmetry/non-symmetry of the left/right inverters in the designed 4T CFET SRAM cell. Thus, the proposed study provides a holistic insight into developing a variability-aware CFET SRAM cell.
AB - Complementary FETs (CFETs) vertically stack n- and p-FETs to achieve superior scaling; however, the confined gate metal thickness induces Metal Grain Granularity (MGG)-related workfunction fluctuations. Using well-calibrated TCAD simulations, this proposed study investigates: (i) the impact of MGG on threshold voltage deviation (σVth), (ii) its influence on the static behavior of a 1T CFET inverter, and (iii) the resulting variability in the static noise margin (SNM) of a 4T CFET SRAM cell. The random grain orientations and boundaries yield σVth of ~10 mV (nFET) and ~9 mV (pFET), resulting in a ±13.2 mV shift in inverter switching threshold (VM) for a 2 nm average grain size (Gr). Consequently, MGG-induced variability significantly degrades SRAM stability, with σSNM rising from 5 mV to 26.3 mV (Read) and from 8.3 mV to 39.7 mV (Hold) when Gr varied from 2 to 8nm. This indicates enhanced variability from reduced boundary averaging, with the Hold state showing greater deviation due to node isolation and positive feedback effects. Furthermore, histograms, QQ plots, and correlation plots have been used to determine the symmetry/non-symmetry of the left/right inverters in the designed 4T CFET SRAM cell. Thus, the proposed study provides a holistic insight into developing a variability-aware CFET SRAM cell.
UR - https://www.scopus.com/pages/publications/105040814565
UR - https://www.scopus.com/pages/publications/105040814565#tab=citedBy
U2 - 10.1109/EDTM65772.2026.11496913
DO - 10.1109/EDTM65772.2026.11496913
M3 - Conference contribution
AN - SCOPUS:105040814565
T3 - 10th IEEE Electron Devices Technology and Manufacturing Conference: Emerging Semiconductor Devices and Manufacturing Technologies, EDTM 2026
BT - 10th IEEE Electron Devices Technology and Manufacturing Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 10th IEEE Electron Devices Technology and Manufacturing Conference: Emerging Semiconductor Devices and Manufacturing Technologies, EDTM 2026
Y2 - 1 March 2026 through 4 March 2026
ER -