TY - GEN
T1 - Study of Electrical Characteristics with different Channel lengths of Bottom gate oxide Semiconductor based Thin Film Transistor
AU - Sannakashappanavar, Basavaraj S.
AU - Rao, Arjun Sunil
AU - Yadav, Aniruddh Bahadur
AU - Khatri, Shreyansh
AU - Garg, Rahul
AU - Prabhat, Kumar
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - This research work focuses on studying ZnO bottom gate thin-film transistors by investigating their electrical characteristics and performance. The simulation of thin-film transistors (TFTs) was performed by using COMSOL Multiphysics 5.6. ZnO is a most promising material for TFTs due to its desirable properties like higher electron mobility and transparency. The design of TFTs involves creating a structural model of the device structure which includes ZnO as active layer, (gate, source, drain) contacts and silicon dioxide as insulating layers. The designed structure is evaluated by studying its electrical behavior by solving Poisson's equation and continuity equation to determine the electron mobility. Various parameters like material properties, dimensions and applied voltages are varied to evaluate the TFTs performance. Important device characteristics like Drain current (Id), Gate voltage and Drain voltage characteristics are studied. The effect of gate voltage on the carrier concentration across source, gate and drain terminals have been evaluated. It was observed that as the gate voltage increases, the electron concentration shifts from drain terminal to source terminal. In addition, the effect of channel length on the drain current has also been evaluated. It is observed that the drain current (Id) of the transistors decreases as the channel length of the transistor increases. This is attributed to the fact that the channel will increase with increase in its length. The comparative study of different channel lengths of 9μm, 10μm and 11μm is analyzed. This work allows the researchers for a practical exploration of ZnO based thin film transistors at lesser dimensions using a powerful simulation tool like COMSOL Multiphysics.
AB - This research work focuses on studying ZnO bottom gate thin-film transistors by investigating their electrical characteristics and performance. The simulation of thin-film transistors (TFTs) was performed by using COMSOL Multiphysics 5.6. ZnO is a most promising material for TFTs due to its desirable properties like higher electron mobility and transparency. The design of TFTs involves creating a structural model of the device structure which includes ZnO as active layer, (gate, source, drain) contacts and silicon dioxide as insulating layers. The designed structure is evaluated by studying its electrical behavior by solving Poisson's equation and continuity equation to determine the electron mobility. Various parameters like material properties, dimensions and applied voltages are varied to evaluate the TFTs performance. Important device characteristics like Drain current (Id), Gate voltage and Drain voltage characteristics are studied. The effect of gate voltage on the carrier concentration across source, gate and drain terminals have been evaluated. It was observed that as the gate voltage increases, the electron concentration shifts from drain terminal to source terminal. In addition, the effect of channel length on the drain current has also been evaluated. It is observed that the drain current (Id) of the transistors decreases as the channel length of the transistor increases. This is attributed to the fact that the channel will increase with increase in its length. The comparative study of different channel lengths of 9μm, 10μm and 11μm is analyzed. This work allows the researchers for a practical exploration of ZnO based thin film transistors at lesser dimensions using a powerful simulation tool like COMSOL Multiphysics.
UR - https://www.scopus.com/pages/publications/105001367563
UR - https://www.scopus.com/pages/publications/105001367563#tab=citedBy
U2 - 10.1109/SILCON63976.2024.10910520
DO - 10.1109/SILCON63976.2024.10910520
M3 - Conference contribution
AN - SCOPUS:105001367563
T3 - 2024 IEEE Silchar Subsection Conference, SILCON 2024
BT - 2024 IEEE Silchar Subsection Conference, SILCON 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 IEEE Silchar Subsection Annual Conference, SILCON 2024
Y2 - 15 November 2024 through 17 November 2024
ER -