Systematic performance benchmarking of nanosheet and FinFET: An intrinsic self-heating perspective

The device miniaturization and engineered structures of non-planar transistors with gate wrapping and channel stacking raise severe reliability concerns. One of the major issues in recent devices is the electrical-thermal interaction of the charge carriers at the confined geometrical active channel region, which causes a self-heating effect (SHE). Thus, systematic measures need to be investigated to standardize the benchmark of emerging devices. Thus, using well-calibrated TCAD models, we thoroughly studied the role of the ambient temperature and SHE in vertically stacked Nanosheet FET (NSFET) and multi-fin FinFET by varying the number of sheets/fins (active channels), while considering the equivalent effective area of both devices. The devices (i.e., NSFET and FinFET) are optimized and benchmarked using the observed figure of merits (FoMs), such as ON current, I_ON-I_OFF ratio, gate capacitance (C_gg), cut-off frequency (f_T), etc. Further, using mixed-mode simulations, the impact of SHE is investigated on an inverter performance followed by realizing the delay and oscillation frequency of the NSFET/FinFET-based three-stage ring oscillator to analyze the frequency compatibility of NSFETs and FinFETs with varying sheets/fins.