The optimized data path ANN for low power and embedded applications

This present work is aimed at the optimization of ANN (artificial neural network) for the low power & embedded applications. Due to rapid switching of the internal signals, power dissipation is very high in the modern VLSI systems. So the optimization is very much essential. This work explores the approaches to modify the existing building blocks of ANN in order to reduce the power (data path optimizations).by considering the 4:2 compressor architecture for the multiplier architecture of layered ANN. The design is modeled using Verilog HDL in the ASIC domain using the CMOS technological library of 65nm.The modified data path architecture consumes 15.91% of area and 26.09% of leakage power lesser when compared with existing architectures. This design provides the better speed up to 12.71%.