The Role of Dielectric Wall in Forksheet FET: Exploring Electrical-Thermal Intercoupling

In this paper, we investigate the role of the dielectric wall (DW) in Forksheet FET (FSFET), to explore the electrical-thermal intercoupling. The DW present between N/P spaces significantly influences the operating mechanism, and the transparency/opacity of the DW raises severe reliability issues. The thermal coupling effect (TCE) is explained by considering the self-heating effect (SHE) at N/P sides individually and with the heat leak through DW, i.e., inter-spaces coupling. Further, the electrical coupling between n/pFET of the FSFET induces the DW capacitance that modulates the rate of carrier inversion on either side. Using well-calibrated TCAD models, we investigate the heat and E-field transfer through DW while considering the DW extension into the channel, resulting in effective I_ON/C_gg modulation. The resultant impact of the proposed assessment is seen on the basic circuit, i.e., a three-stage ring oscillator, is realized for both common and isolated gate configurations. Thus, the proposed guidelines are important in exploring a reliable and robust FSFET design.