TY - GEN
T1 - Unveiling the Role of Interface and Dielectric Wall Traps with Self-heating Induced Aging Prediction of Forksheet FET
AU - Rathore, Sunil
AU - Kumar, Sandeep
AU - Shakir, Mohd
AU - Bagga, Navjeet
AU - Dasgupta, S.
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Evaluating different variability merits is a crucial research step to look after the reliability and aging of the device. Generally, the self-healing effect (SHE) is a prime factor in scaled geometrical devices. In this paper, we performed a SHE-induced performance investigation of the vertically stacked Forksheet (FS) FET. Using well-calibrated TCAD setup, we analyzed: (i) impact of SHE-induced performance degradation on nFET/pFET (self-side) and either side of the dielectric wall (a separating wall between nFET & pFET); (ii) the significance of concentration and location of the trap charges present at Si-SiO2 and sheet-dielectric wall (DW) interface; (iii) the impact of ambient temperature on FSFET; (iv) the prediction of early aging using a well-defined merit of threshold voltage (V_ th ) shift by ±50 mV. Thus, the proposed investigation is worth acquiring the design guideline of a reliable Forksheet FET.
AB - Evaluating different variability merits is a crucial research step to look after the reliability and aging of the device. Generally, the self-healing effect (SHE) is a prime factor in scaled geometrical devices. In this paper, we performed a SHE-induced performance investigation of the vertically stacked Forksheet (FS) FET. Using well-calibrated TCAD setup, we analyzed: (i) impact of SHE-induced performance degradation on nFET/pFET (self-side) and either side of the dielectric wall (a separating wall between nFET & pFET); (ii) the significance of concentration and location of the trap charges present at Si-SiO2 and sheet-dielectric wall (DW) interface; (iii) the impact of ambient temperature on FSFET; (iv) the prediction of early aging using a well-defined merit of threshold voltage (V_ th ) shift by ±50 mV. Thus, the proposed investigation is worth acquiring the design guideline of a reliable Forksheet FET.
UR - https://www.scopus.com/pages/publications/85193240936
UR - https://www.scopus.com/pages/publications/85193240936#tab=citedBy
U2 - 10.1109/EDTM58488.2024.10511703
DO - 10.1109/EDTM58488.2024.10511703
M3 - Conference contribution
AN - SCOPUS:85193240936
T3 - IEEE Electron Devices Technology and Manufacturing Conference: Strengthening the Globalization in Semiconductors, EDTM 2024
BT - IEEE Electron Devices Technology and Manufacturing Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 8th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2024
Y2 - 3 March 2024 through 6 March 2024
ER -