TY - GEN
T1 - Verification of DDR4 SDRAM Using SystemVerilog
AU - Shenoy, Suchitra
AU - Madhushankara, M.
AU - Mathew, Ribu
AU - Basanth, K. P.
AU - Kumar, M. N.Sujan
AU - Nayak, Shridhara
AU - Shetty, Prashanth Kumar
N1 - Publisher Copyright:
© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.
PY - 2025
Y1 - 2025
N2 - An essential part for any digital system is storage. The volatile storage necessitates significant effort in interface design and verification in data-access and preservation. The DDR4 SDRAM is the double-data-rate fourth-generation synchronous volatile dynamic random-access memory with the advantages of large capacity, high speed, low power consumption, and good stability. It is one of the prevalent variants, particularly in the application specific integrated circuits (ASIC) and server market. This work presents the verification of DDR4 SDRAM by elaborating its working in a complete verification environment. The extensive test cases provide a hand book to the verification engineers and building robust infrastructure. The verification of the DDR4 SDRAM is carried out for test conditions using write, read, and burst operations using effective verification environment. The structural and functional coverage of 83.3% provides a good start and further coverage obtained by direct test cases.
AB - An essential part for any digital system is storage. The volatile storage necessitates significant effort in interface design and verification in data-access and preservation. The DDR4 SDRAM is the double-data-rate fourth-generation synchronous volatile dynamic random-access memory with the advantages of large capacity, high speed, low power consumption, and good stability. It is one of the prevalent variants, particularly in the application specific integrated circuits (ASIC) and server market. This work presents the verification of DDR4 SDRAM by elaborating its working in a complete verification environment. The extensive test cases provide a hand book to the verification engineers and building robust infrastructure. The verification of the DDR4 SDRAM is carried out for test conditions using write, read, and burst operations using effective verification environment. The structural and functional coverage of 83.3% provides a good start and further coverage obtained by direct test cases.
UR - https://www.scopus.com/pages/publications/105014432795
UR - https://www.scopus.com/pages/publications/105014432795#tab=citedBy
U2 - 10.1007/978-981-96-5751-3_19
DO - 10.1007/978-981-96-5751-3_19
M3 - Conference contribution
AN - SCOPUS:105014432795
SN - 9789819657506
T3 - Lecture Notes in Networks and Systems
SP - 223
EP - 233
BT - ICT
A2 - Joshi, Amit
A2 - Ragel, Roshan
A2 - Mahmud, Mufti
A2 - Kartik, S.
PB - Springer Science and Business Media Deutschland GmbH
T2 - 9th International Conference on Information and Communication Technology for Competitive Strategies, ICTCS 2024
Y2 - 19 December 2024 through 21 December 2024
ER -