TY - JOUR
T1 - Wavelet transform based fault identification and reconfiguration for a reduced switch multilevel inverter fed induction motor drive
AU - Veerendra, Arigela Satya
AU - Shah, Akeel A.
AU - Mohamed, Mohd Rusllim
AU - Sekhar, Chavali Punya
AU - Leung, Puiki
N1 - Funding Information:
Funding: This work was partially supported by the National Key Research development Program of China (Grant No. 2017YFB0701700). This project was supported by University Malaysia Pahang (UMP) and A.S. Veerendra is working under UMP’s Doctoral Research Scheme (DRS).
Publisher Copyright:
© 2021 by the authors. Licensee MDPI, Basel, Switzerland.
PY - 2021/5/1
Y1 - 2021/5/1
N2 - The multilevel inverter-based drive system is greatly affected by several faults occurring on switching elements. A faulty switch in the inverter can potentially lead to more losses, extensive downtime and reduced reliability. In this paper, a novel fault identification and reconfiguration process is proposed by using discrete wavelet transform and auxiliary switching cells. Here, the discrete wavelet transform exploits a multiresolution analysis with a feature extraction methodology for fault identification and subsequently for reconfiguration. For increasing the reliability, auxiliary switching cells are integrated to replace faulty cells in a proposed reduced-switch 5-level multilevel inverter topology. The novel reconfiguration scheme compensates open circuit and short circuit faults. The complexity of the proposed system is lower relative to existing methods. This proposed technique effectively identifies and classifies faults using the multiresolution analysis. Furthermore, the measured current and voltage values during fault reconfiguration are close to those under healthy conditions. The performance is verified using the MATLAB/Simulink platform and a hardware model.
AB - The multilevel inverter-based drive system is greatly affected by several faults occurring on switching elements. A faulty switch in the inverter can potentially lead to more losses, extensive downtime and reduced reliability. In this paper, a novel fault identification and reconfiguration process is proposed by using discrete wavelet transform and auxiliary switching cells. Here, the discrete wavelet transform exploits a multiresolution analysis with a feature extraction methodology for fault identification and subsequently for reconfiguration. For increasing the reliability, auxiliary switching cells are integrated to replace faulty cells in a proposed reduced-switch 5-level multilevel inverter topology. The novel reconfiguration scheme compensates open circuit and short circuit faults. The complexity of the proposed system is lower relative to existing methods. This proposed technique effectively identifies and classifies faults using the multiresolution analysis. Furthermore, the measured current and voltage values during fault reconfiguration are close to those under healthy conditions. The performance is verified using the MATLAB/Simulink platform and a hardware model.
UR - https://www.scopus.com/pages/publications/85104630607
UR - https://www.scopus.com/pages/publications/85104630607#tab=citedBy
U2 - 10.3390/electronics10091023
DO - 10.3390/electronics10091023
M3 - Article
AN - SCOPUS:85104630607
SN - 2079-9292
VL - 10
JO - Electronics (Switzerland)
JF - Electronics (Switzerland)
IS - 9
M1 - 1023
ER -